Director
Current
Jan 2016 - Present
Who is Mike Clinton? Overview
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Mike Clinton is listed as Director at TSMC at TSMC, based in Austin, Texas, United States. AeroLeads shows a work email signal at tsmc.com and a matched LinkedIn profile for Mike Clinton.
Mike Clinton previously worked as Director at Tsmc and Deputy Director at Tsmc. Mike Clinton holds Msee, Device Physics from University Of Vermont.
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{first}_{last}@tsmc.com
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Profile bio
About Mike Clinton
Over 25 years experience in stand-alone and embedded memory (DRAM, MRAM and SRAM) design projects. Lead designer for multiple 64Mb and 256Mb DRAM products qualified and manufactured by IBM/Toshiba/Nanya/Infineon. SRAM design experience with Texas Instruments at 65nm, 45nm and 32nm technology nodes. Architect for aggressive power management techniques implemented in TI SRAM compiler memories starting at 65nm. Recognized industry expert in variation tolerant SRAM circuit design techniques.Proven record of solving problems and breaking down technical barriers by building teams and working across organizational boundaries.Experience working with teams in various geographic locations throughout the US, Japan. Taiwan, India and Europe and achieving on-time, high quality products and results.* Technical program committee member and joint technology/circuits rump session co-organizer for the 2009 VLSI Circuits Symposium (Kyoto, Japan).* Invited speaker Southern Methodist University, CS/EE forum to give talk on deep sub-micron design challenges (Dallas, TX - Jan. 2009).* Invited speaker at the Dallas chapter of IEEE Circuits and Systems, to discuss SRAM design and variability (Dallas, TX - July 2008)* Microprocessor Forum presenter (“Transistor Variability in Nanometer-Scale Technologies”) at the International Solid-State Circuits Conference (ISSCC) (San Francisco, CA -Feb 2008).* Speaker at a C2S2 (Center for Circuits and Systems Solutions) Workshop on SRAM design held at the Massachusetts Institute of Technology (Cambridge, MA - Oct 2007).Specialties: * Panelist for the technology session (“Who will keep SRAM scaling alive by 2012: Designers or Technologists?”) at the VLSI Technology Symp. (Honolulu, HI - June 2008).* Short Course presenter (“Design for Variability in Logic, Memory and Microprocessors”) at the VLSI Circuits Symp. (Kyoto, Japan - June 2007).* Tutorial presenter (“Anatomy of Variability and Making “Variation Tolerance” Vaccine in Nanometer Technologies”) at the Design Automation Conf. (DAC) (San Diego, CA - May 2007).
Listed skills include Cmos, Eda, Circuit Design, Ic, and 26 others.
Current workplace
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10 roles · 37 years
Mike Clinton work experience
A career timeline built from the work history available for this profile.
Feb 2013 - Jan 2016
Analog Division - Senior Member Technical Staff
SRAM, FRAM and ROM design for Analog Products
Mar 2010 - Feb 2013
Kilby Labs - Senior Member, Technical Staff
* Researcher working on ultra low power circuit and memory design techniques.
Jan 2009 - Mar 2010
Backplane Technology Center - Senior Member, Technical Staff
* As lead designer, I collaborated with technologists to develop the industries smallest 45nm SRAM bitcell.* We analyzed and made trade-offs to optimize for area, leakage and read/write margin.* Proposed and analyzed various circuit options to improve the operating window of the 45nm SRAM bitcell. Bridging between the needs of the memory compiler library team and customers, and the technologists.* Extended the aggressive power management techniques introduced with the 65nm memory compiler library to 45nm, and introduced new techniques which enabled TI to get to the next level in leakage savings.* Part of the tech transfer team working with our foundry partner at the 40nm high performance node. My role was to evaluate the sram bitcell (power, performance and read/write margin) and make sure TI quality requirements were met.* Helped define the 32nm SRAM bitcell design point (area, power, performance, r/w margin and variation tolerant circuits techniques).
Sep 2005 - Jan 2009
65Nm Sram Memory Compiler - Senior Member, Technical Staff
* Early bitcell evaluation and compiler definition.* Architect for aggressive power managment techniques. Assembled a team from the US, India and Japan to design and fan-out these techniques across the entire 65nm LP and HP compiler memory library.* These memories enabled the first and lowest power baseband processors in the industry at 65nm.
Sep 2002 - Sep 2005
Mram Design - Senior Engineer
* Design manager for the IBM/Infinion MRAM design alliance product design group.* Worked with IBM Research and internal IBM customers to define MRAM product space and appropriate product demonstrator.
Sep 2001 - Sep 2002
Dram Design - Senior Engineer
* DRAM design as a member of the IBM/Infineon/Toshiba Design alliance.* Lead design experience for qualified DRAM products which went into production on three continents.* These products included; 64Mb EDO, SDRAM and DDR products, 128Mb SDRAM product, 256Mb SDRAM and DDR products and a 512Mb DDR2 experimental design.* Individual design responsibilities for row path, column path, data path, voltage generators, row and column redundancy, test mode state machine and as well as design of various test modes, and adress transition detect (ATD) circuits.* Participation in the initial standardizations of synchronous DRAMs at JEDEC.* Technical interface to internal IBM customers in PC, AS400 and mainframe business lines.
1990 - 2001
~11 yrs
Senior Design Engineer/Manager
* A member of the original Sematech Start-Up team * Responsible for staffing the design team and defining the CAD and workstation environment for the design group.* Responsible for the circuit related yield learning in order to ramp the IBM 4Mb DRAM product in the Sematch fabs. This responsibility was ended when it weas decided that Sematech only required the backe-end process (the chem-mech polish and palnarization).* Design leader and contractor interface for 0.5um and 0.35um manufacturing demonstration vehicles (MDV's).
Jul 1988 - Jun 1990
Dram Design - Staff Engineer
* 256kb NMOS DRAM design* 4Mb CMOS DRAM design (first CMOS DRAM design at IBM, and first DRAM design with a 3-dimensional trench capacitor).* Responsible for voltage generator design and the data path design (which was the industry first DDR design getting data on both edges of the clock).* This design was qualified and enabled unprecedented performance gains in the IBM Mainframe memory sub-system, due to the novel data path design.
Jul 1982 - Jul 1988
3 education records
Mike Clinton education
Msee, Device Physics
University Of Vermont
Bachelor Of Science (Bs), Electrical And Electronics Engineering
Lehigh University
Education record
Waldwick High School
FAQ
Frequently asked questions about Mike Clinton
Quick answers generated from the profile data available on this page.
What company does Mike Clinton work for?
Mike Clinton works for TSMC.
What is Mike Clinton's role at TSMC?
Mike Clinton is listed as Director at TSMC at TSMC.
What is Mike Clinton's email address?
AeroLeads has found 1 work email signal at @tsmc.com for Mike Clinton at TSMC.
Where is Mike Clinton based?
Mike Clinton is based in Austin, Texas, United States while working with TSMC.
What companies has Mike Clinton worked for?
Mike Clinton has worked for Tsmc, Texas Instruments, Ibm, and Sematech.
How can I contact Mike Clinton?
You can use AeroLeads to view verified contact signals for Mike Clinton at TSMC, including work email, phone, and LinkedIn data when available.
What schools did Mike Clinton attend?
Mike Clinton holds Msee, Device Physics from University Of Vermont.
What skills is Mike Clinton known for?
Mike Clinton is listed with skills including Cmos, Eda, Circuit Design, Ic, Low Power Design, Sram, Microprocessors, and Analog.
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