1000+ MGate asic designs in TSMC16/6nm for high bandwidth ethernet switch/router chips. Responsible for design of switch fabric control. Architecture and design of a pipelined SRAM handler for high rate, multiple ALU, statistical RmW. Created patent level algorithms and design for traffic shaping (high speed arithmetic functions). System and RTL design of hierarchical cpu control structures including dma, event and interrupts. Intricate design for measuring time and latency with 50ps resolution. Various designs involving: BISTs/Test vector routing/Clock synthesis/Chip top level routing/PVT measurements/etc

Lead designer CPU interfaces. Several designs in TSMC 28nm asics for 200Gb/s ethernet, including arithmetics, caches and ring-bus structures at very high rates. Prototyping using top-end Xilinx FPGAs, enabling hardware and software co-verification before the asic is manufactured. Defining boot sequences, embedded cores and pushing sw/hw-performance.

Designing a 20Gbps Video-on-demand server. Several Altera FPGA designs including AES and MD5 crypto, BCH error-correcting-coding, packet classification, multi-channel DMA, metering/shaping of traffic as well as various high-speed interfaces and BIST's. Designing drivers, apps and debug in C/Linux.

Designing a 40Gbps network processor (100Mgate+). Responsible for generic DDR-SRAM / FCRAM / RLDRAM / NSE / CAM programmable interfaces, handling i/o at 530Mbps/pin. Also designed co-processor in Xilinx FPGA handling high performance shaping and metering.

Contract with Ericsson Telecom in Älvsjö, Stockholm 2001-2002.Designing a voice processing ASIC. Designing high performance arithmetic blocks. Used Celaro hardware acclerator for verification. Contract with Saab Avionics, in Kista, Stockholm 1997-2001.Designing a graphics processor ASIC for the Gripen fighter jet. Tool support and contacts with vendor. Several Altera FPGA designs for video processing as well as C++ code in embedded VxWorks environment. Supervising several projects as senior designer as well as giving giving courses and lectures. Contract with Ericsson Communication Systems, Lund 1996-1997.Asics for GSM and AMPS mobile phones. Low voltage and low power design. Responsible for deep-submicron design flow, and handled libraries and contacts with vendor. Synopsys tool support. Using VHDL and several Mentor Graphics tools. Contract with Ericsson Telecom, Stockholm 1993-1995.Designing SDH telecom equipment using Motorola 0.5u asic technology (300+ kgates), in Verilog and Synopsys environment. Several designs, also responsible for generating functional test vectors and ATPG vectors.

Four Texas Instruments asics. Modem designs for laptops (analog design/real-time assembly programming). Parking meters (battery chagers/power supply).

Giving course: 'Communication Theory and Systems' for final year telecom. students. Supervising BA students electronics projects.