Mandar Bhoir Email & Phone Number

Mandar received his PhD from Dept. of Electrical Engineering, Indian Institute of Technology Gandhinagar (IITGN), India. He had been a Visiting Research Scholar at Interuniversity Micoelectronics Centre (IMEC), Belgium, Japan Advanced Institute of Science and Technology (JAIST), Japan and Indian Institute of Technology Kanpur (IITK), India. He received his Master of Technology (M.Tech) from Dept. of Electrical Engineering, IITGN, India in 2015 and Bachelor of Engineering (B.E) from Dept. of Electronics Engineering, K. J. Somaiya College of Engineering (Mumbai University), Mumbai, India in 2013.His research interests include investigation of advanced CMOS devices from the perspective of physics, technology, electrical characterization, simulations and device modeling. He has studied process-induced variability in sub-10nm fin-width FinFETs and provided a systematic strategy to separate the impact of different variability sources from electrical measurements (collaboration with IMEC, Belgium; published in IEDM 2019). He has also worked on analysis and modeling of UTBB FD-SOI MOS transistors (collaboration with CEA-LETI, France and IITK, India). He was also responsible for indigenous development of LDMOS process-flow compatible with SCL’s 180nm CMOS technology (collaboration with SCL, Dept. of Space, Govt. of India) in a cost-effective manner.

Listed skills include Sentaurus Tcad, Cadence, Embedded Systems, Microcontrollers, and 17 others.