Sanjeev Sukumar M Email & Phone Number

Bengaluru, Ka, In

Bengaluru, Karnataka, India

Bangalore

ASIC top level development:• Integrating all Sub-components of the ASIC at top level and make connections between the components appropriately• Generate Tap controller module and implemented ejtag chain for test mode debugging• Sync up with DFT hook up team and sub-component owners to make sure test mode configuration is implemented properly• Implemented Scan muxes and for all clocks and resets to work for test and functional mode• Understand CSU/DCSU and Clock gen modules and implemented clock gating circuitry at different levels• Sync up with Orbit IO team and analog components teams for monitoring Power IO's• Verification issues debug and coverage closure for the top level.• ECO changes implemented post RTL Freeze.• Review and analysis of CDC using Spyglass, Synthesis logs, LEC logs, Clock & Reset tree.Device virtual port:• Worked on Enhancements wrt virtual port• Wrapper module implemented for virtual port IP to support additional enhancements• Verification and coverage closure for the wrapper module• Config guide updates required for the Virtual port

Bengaluru Area, India

Bengaluru Area, India

Bengaluru Area, India

Ethernet 10G IP development1. Understand the protocol and design Architecture discussions with Architect2. Documenting the FSM for each of the modules and cross verifying with the client3. Documenting top level and module level pin diagrams and verified with Architect4. RTL development as per the Architecture and as per the Guidelines document provided the Client.5. PTP(Precision time protocol) Implementation as a feature update.6. Generating spyglass & DC results and sharing them with the client for review as required7. Resolving the design issues and updating the design architecture for potential issues.8. Involved in developing DC/Spyglass constraints and Spyglass waivers as required.9. Developing new features addition.

Bangalore

Bangalore

1. Design analysis in respect to speed, area, logic elements with different options in regards to technology, I/O interfaces and IP features for PCI express IP2. Automating the SDC file generation for different IO interface

Worked on proprietary bus protocols. Worked on NC Sim, Synopsys LEDA, Synplify Pro

Hyderabad Area, India

Chennai Area, India

Worked on System level and Module level Design and Verification.Expertise in using Xilinx ISE, Altera Quartus tools.Expertise in Verilog HDL and KNowledge of VHDL and System Verilog languages.Validated Opencores Ethernet 10/100 code on Stratix II GX boardWorked on Network Protocols Ethernet, Serial ATA, ARINC 818Knowledge of AMBA AHB,Wishbone,Avalon, I2C, UART bus protocols.Worked on NIOS II Processor.

Teaching Digital Design, Verilog HDL, VHDL languages, FPGA Architectures.

Master Of Technology (M.Tech.)

Be

Education record