Muhammad Imran Email & Phone Number

Spain

• Actively involved in the development and execution of (VEC) the accelerator chips (EUPILOT Project), focusing on enhancing system-level performance through advanced C programming and testing methodologies.
• Contributed to the final-stage debugging of integration issues and core bugs in SOC Cincoranchinvolving the BSC Lograto Ka core (PERTE Project) using pre-generated binary testing to ensure operational integrity.
• Collaborated with cross-functional engineering teams to identify and resolve hardware integration faults, enhancing system efficiency.

• Integrated proprietary CXL 0.3 and PCIe 6 IPs with Turchip VIP, ensuring compatibility and optimal performance within the verification environment.
• Contributed to the bring-up process for PCIe Gen 1 link, demonstrating the functional capability of the integrated IPs and verifying their operational readiness.
• Developed test plans for CXL 3.0 and PCIe to ensure robust validation and compliance with standards.
• Verified open-source AMBA bridges utilizing Synopsys VIP to verify RTL designs for AMBA bridges (AHB-Lite to APB and AXI to AHB), ensuring functional correctness and performance.
• Bridge IP verification involves the complete verification process of bridge IPs, including VIP integration, testbench development, and crafting UVM tests to achieve coverage closure.

Punjab, Pakistan

• Gate-level simulation (GLS) testing for SemiFive's ARIES and WARBOY SoCs.
• Performed extensive debugging and C-based regression testing to ensure the ARIES and WARBOY SoCs met design specifications and added C tests to achieve higher interface and functional coverage.
• Onboarding of Cadence eMMC Host Controller and RTC IPs with open-source Rocket-chip core via SiFive onboarding flow on SOC Level, developing Testplan and writing directed C test cases for interface and functional.
• Developed UVM agents to handle clock, reset, BOOT Interface, Side-band Interface, and IO-PAD for Cadence eMMC Host Controller within the IP integration for SoC environments, providing proper synchronization (via.

Lahore, Punjab, Pakistan

• During my training, I gained expertise in various subjects, including Verilog, SystemVerilog, Scala, Chisel, Computer Architecture, RISC-V processors, and C/C++, as well as Communication Skills. Moreover, I actively.
• Developed the PMP (Physical Memory Protection) unit for the SiFive E21 core equivalent in SystemVerilog and verified its functionality.
• Implemented an RV32I-based Instruction Set Simulator (ISS) for the SweRV-EH1 core and verified its accuracy using a layered testbench environment.
• Conducted verification of the Wishbone slave protocol utilizing a layered testbench methodology.
• Designed Designed a RISC-V three-stage pipelined processor.