Muhammad Sarwar Email & Phone Number

Manchester, Nh, Us

-Professional industry standard memory IP design expert.-Developed SRAM and ROM IPs from scratch for Allegro's BCD/CMOS 0.18um process to use in RISC-V processor within mixed signal design.-Guided layout engineers to make layout area, power and timing efficient.-Hands on experience using Liberate tool to characterize memory IPs-Experienced identifying the root cause of silicon bugs and provided potential solution to it.-Developed test chip to characterize the SRAM and ROM bit cells and IPs using memory controller and I2C interface. -Developed 0.18um compatible EEPROM IPs which significantly reduces the area by eliminating interface elements to 1.8v digital controller.

Manchester, Nh, Us

Responsible to manage the volatile/nonvolatile memories.. Designed and Developed High voltage driver circuitry for a 32KByte NOR Flash Memory using Allegro's NVM technology.. Developed Test Qual vehical to validate 32KByte flash memory. • Managing a design team, allocating resources and projects.• Responsible for mentoring design engineers and providing recommendations on volatile and nonvolatile memory circuit design, layout and test methodologies. • Tracking schedules and setup milestones.• Staffing teams appropriately and distribute responsibilities within the group.• Developing new competencies within the Design group to handle new technologies, EDA tools and verification methods.• Working closely with several foundries to define and design the process flow for non-volatile memories.• Working with various IP and design vendors to get outstanding jobs done efficiently in a cost effective way

Manchester, Nh, Us

Was responsible to Design and Characterize EEPROM, SRAMs and ROMs that have been used in our Allegro’s mixed signal designs.• Designed (Transistor Level) and characterized EEPROMs, SRAMs and ROMs for 32 bit ARC processor using cadence flow and delivered complete characterized IP( Design, Layout, Verilog, Liberty and Lef) to allegro’s sensor and Power IC group.• Evaluated and adopted Magma’s Siliconsmart characterization tool to Allegro’s flow to characterize standard cells and memory IPs.• Designed and characterized ROM(64x6) using cadence flow and incorporated in SOC flow both for place and route and timing analysis in ASIC Sine Wave generator using BCD5 process.• Designed and Characterized SRAM(1024x16) using cadence flow and incorporated in SOC flow both for place and route and timing analysis in ASIC Sine Wave generator using BCD5 process.• Developed and characterized Standard Cell Library using cadence tools that include Analog Design Environment, Virtuoso XL, Abstract Generation and ELC( Encounter Library Characterization).• Designed of an ASIC/FPGA for 16 bit Sine Drive. Verilog/VHDL code was written and simulated using Verilog/VHDL –XL, Synthesized and optimized using First Encounter Flow.• Developed workshop for RTL Compiler, First Encounter and Assura/QRC parasitic using Allegro’s BCD5 process.

Manchester, Nh, Us

1. Was responsible to develop and maintain physical verification and Parasitic extraction flow at Allegro using cadence Assura and QRC tool. 2. Was responsible to maintain and support Synthesis and P&R tool.3. Study and research the importance of the parasitic resistance, capacitance, inductance and mutual inductance effect for the 0.35 um SG5 (Allegro, Sanken, Polar Fab) process.4. Developed parasitic extraction algorithm for the SG5(Allegro) process using Cadence Assura Parasitic Analysis tools.5. Designed of a Phase lock loop circuit using Allegro’s abcd4/d6/h4 process that works up to a frequency of 240MHz.

Virginia Beach, Va, Us

1. Taught students Digital Electronics.2. Taught students Introduction to Communication Systems.3. Taught students AC/DC Circuits and Electronics.

1. Was responsible for instructing students in Digital Electronics, Microprocessors, Electronic Devices and control systems (PLC), DC/AC Electronics. 2. Taught students about 68HC11/8051 microprocessor and assembly language. 3. Taught the programmable Logic Controller using Allen Bradley SCL 500/02. 4. Instructed and supervised students during laboratory period to assist in their understanding of topics covered in the class. Assisted students in troubleshooting and resolving their laboratory problems and difficulties. 5. Was Responsible for creating weekly lesson plans and preparations for each lab. Helped students to design and implement capstone projects that reflect the culmination of skills learned in the CEET program.

1. Designed of 250Mhz 12-bit DAC.2. Designed of power on reset circuit, Crystal Oscillator circuit.3. Designed of two stage Opamps with current reference circuits. Specs: offset 52mv, open loop gain=60dB, UGB=3Mhz, CLoad = 10pf. All specifications have been verified using cadence Analog Design Environment.

San Jose, California, Us

1. Analog design Environment & Virtuoso Layout Editor.2. Design Rules & LVS check using Assura.3. LVS Rules development and maintenance.

Msee, Microelectronics

Bachelor Of Science (Bsc), Electrical And Electronics Engineering