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Passionate and experienced senior test engineering professional who specializes in SOC/MEMS Automatic Test Equipment (ATE) NPI Test Programs for high accuracy (16/18 Bits) Mixed Signal Data Converters DACs, MEMS IMU (Gyro+Accel) and Analog devices at Wafer Sort Level and Final Test Level, using industry-standard ATE testers such as LTX-MX, KVD, Credence ASL1K/3K, Teradyne, Catalyst, NI PXI Controller and Motion Sense ATEs.• Drove high-volume production of TDK-InvenSense's 6-axis IMU products, including NPI and legacy products. Achieved exceptional WS and FT yield (>97%) across all stages. Streamlined test processes, exceeding company targets by reducing test times by 30-40%.• Optimized FT Test Time on Samsung HVM YOK products ICM-42605M/-42631 family by 48%. • Developed comprehensive DS Test Coverage IP Solutions for Digital, Analog, Mixed-Signal, I/O, Memory, DFT Functional test utilizing robust and repeatable test methodologies for HVM WS/FT releases and offshore transfer.• Design and Developed and Optimized Multi-site and Modular Advanced OTP Trim Routines. • Enhanced data sheet test coverage for major customers (Meta, Samsung) with screen tests for DMP-SRAM memory, high-frequency functions, and identified gaps.• Created high-resolution FIFO tests coverage (16-19 bit) for TDK's XAN ICM-45686 IMUs for AR/VR, wearables and IoT.• Improved SW/HW infrastructure and documentation via Atlassian Confluence Tools.• Extremely proficient in developing software applications with OOP using C/C++ and C#.• Recipient of TDK-InvenSense “Sensing Excellence Award” Sensor System on Chip 2021 and 2015.• Innovative Product: 16 bits V/I DAC MAX5661, Finalist Best Innovative Product of the year in “EDN’s 19th Annual Innovation Award 2009”, and MAX5318 18-Bits High Accuracy DAC, Winner of the EE-Times China Annual Creativity in Electronics (ACE), Product of the Year Award 2013.Specialties: Custom Analog / Mixed-Signal SOC / NPI Characterization / Post Si Verification / Wafer Sort / Final Test / MEMS IMU 6-Axis (Gyroscope +Accelerometer) / "CMOS+MEMS Bounded Wafers / BFM / OTP Programming / Laser Trim / SPC / Yield Analysis / Test Time Optimization / Yield Improvement / Cost Reduction / DOE / FA / Production Release / Automation / Offshore Transfer / Multi-site / Modular Program / Load board / Probe Card / PCBA PADS / Allegro / SI & PI / Functional Test Coverage IPs / DFM & DFT / Bench Testing / EDA BFM SW Tools / DFT- ATPG / DVT / Synopsys Controller / Verilog HDL / C/C++ / C# / MATLAB / VB / Agile / Tortoise Git / Atlassian / Jira / Agile / Perl / Python.
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Principal Product Test Development EngineerTdk Invensense Dec 2019 - PresentSan Jose, Ca, UsAchieved high-volume production success for TDK-InvenSense's 6-axis IMUs, including rigorous testing of gyroscopes and accelerometers throughout the manufacturing process. I ensured timely delivery of initial samples and high-quality production runs by developing comprehensive test programs for characterization, qualification, and defect reduction. Additionally, I optimized test processes using NI-PXI and motion ATE, significantly improving efficiency and quality in high-volume manufacturing.• Drove high-volume production of TDK-InvenSense's 6-axis IMU products, including NPI and legacy products. Achieved exceptional WS and FT yield (>97%) across all stages. Streamlined test processes, exceeding company targets by reducing test times by 30-40%.• Optimized FT Test Time on Samsung HVM YOK products ICM-42605M/-42631 family by 48%. • Developed comprehensive DS Test Coverage IP Solutions for Digital, Analog, Mixed-Signal, I/O, Memory, DFT Functional test utilizing robust and repeatable test methodologies for HVM WS/FT releases and offshore transfer.• Design and Developed and Optimized Multi-site and Modular Advanced OTP Trim Routines. • Enhanced data sheet test coverage for major customers (Meta, Samsung) with screen tests for DMP-SRAM memory, high-frequency functions, and identified gaps.• Created high-resolution FIFO tests coverage (16-19 bits) for TDK's ICM-45686 IMUs for AR/VR, wearables, and IoT.• Improved SW/HW infrastructure and documentation via Atlassian Confluence Tools.MEMS Test Development• Reduced IMU DPPM defects with innovative screen tests: FFT filtering for gyros/accel, low power low noise, and ODR routines. • Reduced MEMS stiction qualification & characterization test time by 66.61% (from 4.65 seconds to 1.55 seconds) on a Micro Drop Tester.• SPEA DOT800 ATE WS/FT correlation and buyout.• Devised Innovative Sensing, Optimization & Characterization Techniques: Recipient of TDK-InvenSense “Sensing Excellence Award” Sensor System on Chip 2021.
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Principal Test Development EngineerTdk Invensense Nov 2013 - Nov 2019San Jose, Ca, UsResponsible for Test Development of NPI MEMS Products and Software Test Development of Next Generation IMU (Inertial Motion Units) of Vibrating Gyroscope and Accelerometer at Wafer Scale Package “CMOS Plus MEMS” Bonded Wafer, Final Test and Hardware Development using NI PXI Controller and Motion Controller. • Developed and Released TDK-InvenSense First Round Robin 6-Axis IMU IVY product family ICM20628 and the release of five IMU 6-DOF products TUN, VDM, ATH, ISB, HAV and YOK ICM42605M with Final cumulative Yield greater than 95% and Development of Next Generation of Gyro and Accel. • Design and Develop Digital Functional IP’s and Parametric Test IPs, MEMS Gyro and Accel IPs applicable to all companywide products using vertical integration of Test Development, • Designed and Developed and Optimized Multi-site and Modular Advanced OTP Trim Routines.• Apply Advance Test Time Optimization Techniques reducing WS and FT Test Time by 40%. • Devised Innovative Sensing, Optimization and Characterization Techniques, Received TDK Sensing Excellence Award 2015.
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Principal Test Development EngineerMaxim Integrated Jul 2010 - Nov 2013San Jose, Ca, UsDeveloped New Products Hardware and Software, successful timely release, design reviews, cost analysis, cost reduction, designed and developed Test Strategies and Test IP.• Developed and Released 18 Bits High Accuracy DAC with over 200+ Tests with 94% Yield.• Designed and Developed in a team environment, Multi-site and Modular 18 Bits DAC NPI Products with Advanced OTP Analog Trim Routines, Digital I/O Test, SPI and I2C Timing Tests, SOC Radix and OTP Banks Radix Test, BFM Functional Test using Command and Register Map, Oscillator Frequency Tests, DFT Scan and IDDQ Tests. • Automated Verilog to ATE Bus Functional Model BFM Test, saved 50% Test Development time.• Designed and developed SPI BFM Software Tools with EDA Team for High Accuracy 18 Bits NPI DAC Mixed Signal product and ATE Test Program development using Sidense OTP Memory Controller for storing Device Analog Trimming and Calibration Parameters. These BFM libraries convert Design Engineer’s Task Driven System Verilog encrypted BFM Test Benches into equivalent ATE BFM code using modular, re-usable and parameterized API. • Innovated Cadence Calling C Library for LTX platform that reduce test execution time by 400%.This CCC Wrapper Library innovation allowed direct execution of Design Engineer’s OTP INL and DNL Trim algorithm into Tester language without any conversion, thus saving ATE development Test time and helped time to market. • Devised Innovative Characterization Techniques for MAX5318 18-Bits High Accuracy DAC, Winner of the EE-Times China Annual Creativity in Electronics (ACE), Product of the Year Award 2013. -
Senior Test Development EngineerMaxim Integrated Jul 2001 - Jul 2010San Jose, Ca, UsDeveloped ATE HW & SW for NPI releases, characterization, cost reduction and Offshore Transfer.• Efficiently Release and offshore Transferred Ten New DACs products, three Voltage Reference Products and one Amplifier product with greater than 92% Consistent Yield.• Developed Innovative Laser Trimming Algorithm in C/C++ that not only Optimize Test Time by 50% but also trim to very high accuracy targets, enabling us to improve yield from 62% to 92%.This innovative trim algorithm uses sheet resistivity to compute Optimized Trim Curve for high accuracy targets not achievable by conventional linear trims methods. This innovative development of Laser Curvature Trim was a Patentable Idea. • Innovated Time Optimized Laser Trim Routines, reduced WS Time by 80% on 16 Bit DAC products. This “Linear Predictive Trim Algorithm” optimally trimmed less than 5 micro-volts trim target and uses empirically collected Thin Film Resistors Sensitivity data and lowest laser beam step size of 100 nm on GSI Prober Trim System.• Meticulously worked in developing innovative test characterization techniques for industry first 16 bits V/I DAC MAX5661, which was nominated as a finalist Best Innovative Product of the year award in EDN’s 19th Annual Innovation Award 2009.• Established best practices in the Design and Development of Laser Sort and Final Test HW & SW of Maxim’s NPI High Performance 16 Bits DAC and High Accuracy Reference Products.• Coordinate and work closely with Design Engineering Team from conceptual IOS to High Volume Production Release and Offshore Transfer utilizing High Performance ATE Test Platforms, such as LTX-MX, KVD, TMT-Credence/ ASL3000 and Teradyne Catalyst Testers.• Highlights of Key High Volume Products Released, DB70MAX5318 18Bit DAC, MAX5316 16 Bits DAC, DB21/MAX5661 V/I 16 Bits DAC, DA95/MAX5202 16 Bits DAC, RF50/MAX6070, IC00/MAX1550.
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Senior Software EngineerSierra Wireless / Airprime Inc. Jul 2000 - Jul 2001Richmond, British Columbia, Ca• Developed Embedded Diagnostic, Power on Self-Test (POST) Routines and Air Scope GUI for compact flash CDMA wireless modem using LSI CBP Base Band Processor.• Design and developed AirScope GUI for AirPrime compact flash CDMA wireless modem for Pocket PC / PDA that allows user easy access to Wireless Data / Voice applications using MS Embedded Tools.• Develop Host-Modem Message Library software using Qualcomm chip set and InfoTech UPST for CDG Interoperability wireless device testing. • Developed Diagnostic programs and PowerOn Self-Test (POST) for AirPrime CDMA Wireless modem for HandSpring Visor PDA using LSI CBP Base Band Processor. • Participate in AirPrime prototype CDMA modem testing and evaluation for COMDEX 2000 at Cadence Design Center, Oregon. -
Senior Software EngineerHitachi Apr 1998 - Jul 2000Chiyoda-Ku, Tokyo, Jp• Designed Software for Hitachi Magnetic Disk Optical Inspection RS7000 Manufacturing ATE utilizing OOAD, OOP in C/C++. Developed Substrate Defect Detection and Classification Routines and Disk Defect Plotting Software using MATLAB, helped improved productivity to 98%.• Responsible for software configuration management (SCM), evaluated ClearCase and ClearQuest. • Provide customized version of Optical Inspection Software to Hitachi’s worldwide customers on RS7000 and RS1350 systems.• Participate in the software development and quality improvement process. Extended design capabilities of the ATE software architecture by Reverse Engineering the existing source code, using Rational Rose and UML. -
Senior R&D EngineerRead-Rite Corporation Mar 1996 - Apr 1998Supported Design and Wafer Process teams in Characterization of New MR and GMR head designs, materials and processes in NPI development phase. • Developed Application Software for comprehensive testing of Advanced MR Head using GUZIK WITE32, VB and Microsoft Access database.• Devised tests to investigate Component and Drive Level HDI Reliability Qualification, Electrical, Magnetic and Tribology Characterization of Advanced MR Head and VCR Advanced Media. • Designed tests for Spin Valve devices for Bit Error Rate, Micro Track Profile, Digital Parametric Tests, and PRML Read Channel Optimization.• Conducted Automatic Test Equipment Qualification related to software design and GUI interface.• Designed and developed test methods to investigate Electrical and Tribological performance of the MR and Spin Valve heads. -
Engineer-Ii R&DMicropolos Corporation Aug 1992 - Mar 1996Design and Developed Head and Media NPI Qualification at Component and Drive Level. Developed in house ATE Control Systems for HDI Reliability Accelerated Wear Test at Near Contact Recording.• Developed Data Acquisition and Digital Control System using ABS spindle, HF ADC & DAC Converters and Real Time Controllers. This was used for the study of hard disk interface interaction for Advanced Tomahawk products, saving the company $200,000 in Tribology Tester cost.• Performed head & media EVT and Read/ Write performance characterization using GUZIK RWA.• Actively participated in Design and development of Peak Detection Read channel and Advanced PRML Partial Response Maximum Likelihood Read Channel using SSI 32P4910. • Developed Modeling and Simulation of Embedded Servo Control system using C, MATLAB, Matrix-X and Rose Camp software.
Muhammad Younus Skills
Muhammad Younus Education Details
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California State University, NorthridgeElectrical Engineering -
Ned University Of Engineering And TechnologyElectrical Engineering
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University Of California, Santa CruzCertificate In Object Oriented Programming Using C/C++
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University Of Karachi, KarachiPhysics
Frequently Asked Questions about Muhammad Younus
What company does Muhammad Younus work for?
Muhammad Younus works for Tdk Invensense
What is Muhammad Younus's role at the current company?
Muhammad Younus's current role is Principal Test Development Engineer at TDK InvenSense.
What is Muhammad Younus's email address?
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What is Muhammad Younus's direct phone number?
Muhammad Younus's direct phone number is +171881*****
What schools did Muhammad Younus attend?
Muhammad Younus attended California State University, Northridge, Ned University Of Engineering And Technology, University Of California, Santa Cruz, University Of Karachi, Karachi.
What are some of Muhammad Younus's interests?
Muhammad Younus has interest in Outdoors, Sports, Boating.
What skills is Muhammad Younus known for?
Muhammad Younus has skills like Mixed Signal, Test Engineering, Embedded Systems, Analog, Verilog, Ic, Fpga, Soc, Semiconductors, Electronics, Product Development, Arm.
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