Muhammad Anser Email & Phone Number

Markham, Ontario, Canada

Lead a team of engineers focused on increasing Wafer Sort Yield of AMD Client Products, including both chiplet and monolithic designs (CPU and APU) in advanced technology nodes.

Markham, Ontario, Canada

Worked on Sort Yield Improvement of Radeon RX580/590, Radeon RX 540/550/550X, Radeon 550X, Server CPU (chiplet design). Also responsible for product targeting control and device variability reduction activities.

Toronto, Canada Area

Senior Member of Technical Staff, 2010-2012-----------------------------------------------------------------As foundry interface and technology node owner, managed technology assessment and performance / power / cost trade-off determination to select optimal technology for dGPU and APU products. Developed and maintained infrastructure and methodologies to improve technology characterization and selection process. * Managed foundry interface for TSMC 28nm and 20nm technology, resulting in 3 dGPU and 1 APU products being manufactured in 28nm technology. * Obtained desired technology characteristics for high performance low power products by balancing design team requirements with foundry offering.* Achieved higher Vmax for products by assessing and negotiating product reliability based on predicted product layout, thereby increasing product performance.* Used design critical parameters list to negotiate technology characteristics with foundry, creating optimal device suite and reducing final product cost.Member of Technical Staff, 2008–2010-------------------------------------------------------Identified technology selection for dGPU and APU products using SPICE characterization suites and infrastructure. Provided support for analog and mixed signal design teams. * Co-managed foundry interface for TSMC 40nm and TSMC 32nm technologies for GPU products, resulting in 8 dGPU and 2 APU products manufactured in 40nm technology.* Created SPICE model characterization and QA infrastructure for technology assessment. * Improved first pass design success rate by holding regular meetings with analog and mixed signal design teams and communicating technology changes / updates of impact.* Provided support to designers on individual basis in minimizing number of unique devices for optimal circuit performance at lowest possible cost.

Pocatello, Idaho Area

Project Manager and Process Integration Engineer, 2002–2007------------------------------------------------------------------------------------------Managed process integration projects for analog and mixed signal use in medical, automotive and industrial applications, including defibrillators, pace makers, drive by wire, and washing machine controllers. Interfaced with fabrication, product engineering, reliability, marketing, SPICE modeling, and verification teams. * Achieved $500K wafer cost savings over 1 year period by modifying test vehicle layout. * Modified test vehicle layout to incorporate MIM capacitor in SRAM to enable module qualification, resulting in project schedule pull-in of 6 months. * Performed reliability testing on critical aspects of technologies, including HCI, NBTI, TDDB and VBD. Created wafer level reliability testing methodology which improved turn-around time from 2 weeks to less than 2 days.* Integrated 0.5µm dual gate high voltage and low threshold mixed signal CMOS technology, optimizing high voltage devices and low threshold devices for automotive / industrial and medical mixed signal applications.* Integrated and managed 0.35µm dual gate (3.3 & 5 volts) mixed signal CMOS technology, achieving customer product requirements.* Managed 0.35µm mixed signal CMOS technology on N-EPI substrate with potential for high voltage integration. * Employed SILVACO and ISE tools in determining optimum process conditions, implant profile matching and impact of process steps on performance of technology.Created and implemented electrical and layout design rules consistent with each process, including safe operating area.* Designed and assisted in layout of several test characterization vehicles for process tuning and characterization / modeling activities.

Masters Of Science In Engineering, Microelectronics Photonics

M.Sc., Physics

B.Sc., Mathematics, Physics

Activities and Societies: N/A

Education record