♠Hello! I am a recent graduate actively looking for an opportunity of an entry level Design Verification engineer role in a highly committed organization and develop various test cases for verifying the design and ensure there are minimum number of errors as much as possible. ♠I am good at Digital electronics, Verilog, System Verilog and UVM methodology. ♠I want to utilize my knowledge to strengthen the value of the firm by verifying various RTL codes for designing high efficient products with minimum errors and faults.