Vincent Parrilla Email and Phone Number
Austin, TX, US
Vincent Parrilla's Location
Austin, Texas, United States, United States
Vincent Parrilla's Contact Details
Vincent Parrilla work email
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Vincent Parrilla personal email
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Vincent Parrilla phone numbers
About Vincent Parrilla
Provided contract/consulting design and verification services for large scale, next generation Application Specific Integrated Circuits (ASIC). Worked extensively with UNIX based tool systems and programs, along with several high level Hardware Design Languages (HDLs).Specialties: Have been part of numerous hardware development teams for development, integration, simulation and functional verification of next generation ASIC components (SOCs). In addition, have gone through an equal number of successful "tape outs". Skill sets include UNIX tools and scripts, perl, C++, Verilog, VERA, SystemC, SystemVerilog, etc. Currently working with OVM/UVM methodologies.
Vincent Parrilla's Current Company Details
Microsemi
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Senior Design Verification at Microsemi
Austin, TX, US
- Website:
- microsemi.com
- Employees:
- 1555
Vincent Parrilla Work Experience Details
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MicrosemiAustin, Tx, Us
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Senior Design VerificationMicrosemi Dec 2012 - PresentAliso Viejo, Ca, UsDesigned, setup and integrate UVM components into company's SOC verification testbench environment.
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Design Verification EngineerSynaptics Feb 2012 - May 2012San Jose, California, UsDesign Verification Engineer - working with verifying touch pad controller cache memeory. -
Senior Design VerificationAmd May 2011 - Jan 2012Santa Clara, California, UsDesign Verification Engineer - working with advanced DDR controller within an OVM environment. -
Senior Design Verification Engineer - Mutt Logic ServicesIbm Global Services Dec 2009 - May 2011Armonk, New York, Ny, UsDesign Verification Engineer - Worked with various in house design modules and standardized components. Test Plan and Testbench development, scripting and regression. DRAM DDR controller, ECC testing, I2C protocols and numerous other infrastructure module verification. HDL Language SystemVerilog - basic OVM infrastructure. -
InvestorLive Oak Brewing 1995 - 2011Investor and patron of the art.
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Verification EngineerIntrinsix - Texas Instruments Apr 2008 - Oct 2008Fort Worth, Texas, UsTest bench development in System Verilog. Legacy test verification. PCI-Express. OVM planning -
Verification EngineerRaza Microelectronics Jul 2007 - Apr 2008Contract EngineerDDR Verification Development. Test plan creation and execution. Testbench development and code extension with VERA using an RVM type structured format.
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Verification EngineerSolarflare Communications Mar 2007 - Jun 2007Irvine, California, UsContract EngineerTest bench infrastructure work, test plan and test development within various blocks of network switch. High-level, system testing. PCI-Express analysis. Verilog-2001, PLI calls, perl and shell script development -
Verification EngineerNeteffect Jan 2004 - Feb 2006UsContract EngineerPart of the verification team to setup verification infrastructure and test methodology for a new SOC design. Developed test bench methodology and verification infrastructure. Script deployment for a very robust regression system for both unit level and full chip components. Test planning, System C, verilog, PCI, PCI-X and PCI-Express, C++, perl, Makefiles and shell script development. -
Verification EngineerStretch Inc. Feb 2003 - Nov 2003Sunnyvale, Ca, UsContract EngineerSetup verification infrastructure and test methodology for a new SOC development. AMBA bus components including high speed/low speed buses, various peripheral components and a core engined powered by an Xtensa CPU. Created numerous VERA based bus functional models and transactors in self checking verification structure. Script development for a very robust regression system for both unit level and full chip components. Test planning, VERA, verilog, C, NC sim, perl, Makefiles and shell development. -
Verification EngineerBroadcom Sep 2002 - Feb 2003Palo Alto, California, UsContract EngineerDevelopment and rework of VERA/verilog based DV test bench environment for network switch Extended existing models and setup regression scripts for verification. New functional features and debug of leveraged environment. Code coverage analysis with VCS. -
Verification EngineerMaple Optical Networks Sep 2000 - Feb 2002Contact EngineerVerification Methodology, setup and development. Helped established a complete test bench infrastructure architecture with Specman (Verisity) based test system. Setup included developing tightly integrated verification handler perl scripts. Created numerous test cases and regression suites. VCS, PLI, perl, and shell development.
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Verification EngineerMaple Optical Systems 2000 - 2002Verification Methodology, setup and development. Helped established a complete test bench infrastructure architecture with Specman based test system. Setup inlcude developing tightly integrated verification handler perl scripts. Created numerous test cases and regression suites. VCS, PLI, perl and UNIX shell development.
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Verification EngineerRedwave Feb 2001 - Sep 2001Contract EngineerVerification Methodology, setup and development. Complete infrastructure architecture for Vera based test system. Established DV flow by integrating specialized perl scripts developed by the applicant. VCS, perl, Makefiles and shell development.
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Verification Engineer3Dfx Apr 2000 - Dec 2000UsContract EngineerVerification Methodology, setup and development. DV infrastructure design and enhancement within existing structures for a Memory Controller used in graphics engine. VCS, perl, Makefiles and shell development. -
Senior Hardware Verification EngineerNokia Oct 1998 - Feb 2000Espoo, Southern Finland, FiContract EngineerDesign verification and script development on backbone router. Complete DV methodology development and test suites. Packet generation and PCI bus integration. Mixed VERA/verilog test bench perl and shell development. -
Verification EngineerChromatic Research Mar 1998 - Aug 1998UsContract EngineerDesign Verification and script development. Created Design Verification Proposal, test plan and procedural documents. Developed test bench, vectors and scripts for automated verification flow for graphics engine. -
Design VerificationCisco Systems Nov 1997 - Apr 1998San Jose, Ca, UsContract EngineerVerification and script development. Test suites and packet data generation on high speed Ethernet controller. VCS/verilog based test bench -
Design EngineerOak Technology Aug 1997 - Oct 1997UsContract EngineerDVD front-end design, simulation and synthesis for 105 MHz data streaming and Synchronization. Test bench development and stimulus vector generation. Verilog-XL simulation toolset. -
Design And Verification EngineerNational Semiconductor Jun 1997 - Sep 1997Contract EngineerDesign and verification of digital subsection within LMC6990. Tasks included RTL development, simulation and synthesis using National standard cell library. -
Verification EngineerCompaq May 1997 - Jun 1997Houston, Texas, UsContract EngineerTest and verification of SNet packet data transactions within the Butte ASIC. Verilog test development and UNIX scripts for stimulus and verification. -
Senior Asic EngineerHigh Level Design Systems Sep 1996 - Jun 1997Contract EngineerSynthesis consultant for EDA floor planing company. Evaluation and structuring of dc_shell and UNIX script files for use in synthesis data acquisition.
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Design EngineerPhilips Oct 1996 - May 1997Amsterdam, Noord-Holland, NlContract EngineerDesign, simulation, synthesis within a MIPS R3000 based Digital Video decoder chip utilizing the MPEG2 standard. Bus interface gateway between internal processor bus and SDRAM controller. -
Design VerificationSynopsys Oct 1995 - Nov 1996Contract EngineerDesign, implementation, synthesis and simulation of various FPGA's within Synopsys' IKOS product line.
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Senior Asic EngineerAmd May 1994 - Oct 1995Santa Clara, California, UsContract EngineerK5 processor development and synthesis. Critical path analysis, Verilog RTL restructuring and speed enhancement techniques using dc_shell. Scripted and automated many design flow processes.
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Senior EngineerIntel Nov 1993 - May 1994Santa Clara, California, UsContract EngineerDesign, synthesis and verification of Pentium Cache/Memory bus controller utilizing the MESI protocol. VHDL RTL development and optimization using dc_shell. Critical path analysis -
Design EngineerAmd Dec 1992 - Nov 1993Santa Clara, California, UsContract EngineerDevelopment on AMD's 486 uP processor. VHDL top-down design of Power Management block. Simulation, synthesis and optimization with Synopsys tool sets including extensive static timing analysis and script development.
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Design EngineerKaiser Electronics Aug 1992 - Dec 1992Contract EngineerVideo display upgrade utilizing i960 processor core. VHDL top-down design strategy, circuit modeling and simulation.
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Design EngineerTexas Instruments Feb 1992 - Aug 1992Dallas, Tx, UsContract EngineerDesign of "Heads-Up" video display gate array. LISP style design and synthesis. META to VHDL conversion and logic synthesis using Synopsys dc_shell. -
Design EngineerAdaptive Corporation Dec 1991 - Feb 1992Contract EngineerDeveloped simulation methodology and test suite for Asynchronous Transfer Mode network switch. Fiber optic front end and circuit modeling on Quicksim toolset.
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Design EngineerNcr Corporation May 1991 - Oct 1991Atlanta, Georgia, UsContract EngineerDesign on "Galileo" Workstation. Intel's 80486 processor L2 Cache Controller, with IBM Micro-channel bus. "Test Plan" and simulation scripts for system verification. -
Senior EngineerTexas Instruments Jun 1990 - May 1991Dallas, Tx, UsTexas Instruments - Information Technology Group: Austin, TX June Contract EngineerStandard Cell and test simulation support. Test plan, test vectors for TI's MC68040 based microcomputer with UNIX engine. Areas include LAN controller, DRAM memory interface and SCSI controller port.
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Senior EngineerTexas Instruments Feb 1990 - Jun 1990Dallas, Tx, UsContract EngineerPrimitive component library programing, HDL modeling and simulation of Standard Cell library. Testing and simulation suite development for a variety of ASIC design platforms.
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Design EngineerHoneywell Aerospace Feb 1989 - Feb 1990Charlotte, North Carolina, UsContract EngineerEnvironmental Systems involved with MD-11 aircraft "weights and balance" avionics. Analog data acquisition interface HCMOS control logic. Fault and "worst case" analysis. Test rig set-up and product production specifications. Additional work with environmental computer circuitry. High energy ESD and lightning protection circuits. PSPICE and C language programming. -
Design EngineerGte, Phoenix, Az Feb 1988 - Jan 1989Contract EngineerTelecommunication control switch redesign. Hardware upgrade for PBX time/space/time switch. Real-time signal routing and error checking of PCM encoded data. ASIC switch memory structure, multiplexing hardware and FDDI interface.
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InstructorMesa Community College Sep 1986 - Jun 1988Mesa, Az, UsPart time instructor in the Physical Science Department community college. Instructed entry level engineering course in computers and programming with MSDOS and FORTRAN.
Vincent Parrilla Skills
Verilog
Systemverilog
Asic
Soc
Fpga
Perl
Functional Verification
Vhdl
Simulations
Tcl
Open Verification Methodology
Systemc
C++
Unix
Linux
Simulation
Pcie
Scripting
Ncsim
Shell Scripting
Modelsim
Integration
Vcs
Ovm
Uvm
Veritas Cluster Server
Vincent Parrilla Education Details
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Arizona State UniversityElectrical Enginnering -
Youngstown State UniversityElectrical Engineering
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Youngstown State UniversityMathematics
Frequently Asked Questions about Vincent Parrilla
What company does Vincent Parrilla work for?
Vincent Parrilla works for Microsemi
What is Vincent Parrilla's role at the current company?
Vincent Parrilla's current role is Senior Design Verification at Microsemi.
What is Vincent Parrilla's email address?
Vincent Parrilla's email address is vp****@****.rr.com
What is Vincent Parrilla's direct phone number?
Vincent Parrilla's direct phone number is +141526*****
What schools did Vincent Parrilla attend?
Vincent Parrilla attended Arizona State University, Youngstown State University, Youngstown State University.
What are some of Vincent Parrilla's interests?
Vincent Parrilla has interest in Kayaking, World Travel, Skiing, Hiking, Amateur Chef.
What skills is Vincent Parrilla known for?
Vincent Parrilla has skills like Verilog, Systemverilog, Asic, Soc, Fpga, Perl, Functional Verification, Vhdl, Simulations, Tcl, Open Verification Methodology, Systemc.
Who are Vincent Parrilla's colleagues?
Vincent Parrilla's colleagues are George Athens, Offie Budinsky Budinsky, Jose Orozco, Bob Hamilton, Foster Adjei, Amrutha Rai, Xiaoyan Li.
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