Main Project Features: This project involves ATPG Stimulation for design_top.Activities performed: ATPG for the glenshee and eaglecrest design. Assisted in simulation debugs for serial runs.

Inserted scan for the partitions and chiplet of T264.Done NA checks for the partition and chiplet level.Done post feflat xclamp flow to avoid xleaks.Done Design Auditor checks for the partition and chiplet level

Main Project Features: Insert scan, generate patterns and simulate for the Mihir SOC.Activities performed: Inserted scan for the blocks in the Mihir SOC and validated it with the patterns. Worked in backend for the Mihir top scan insertion. Simulated the Zero delay and SDF simulations for both MIN and MAX corners for the blocks and top.