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Matt Weber Email & Phone Number

Senior Developer at Akuna Capital
Location: Altoona, Wisconsin, United States 8 work roles 2 schools
1 work email found @akunacapital.com LinkedIn matched
✓ Verified Jun 2026 4 data sources Profile completeness 100%

Contact Signals · 1 work email

Work email m****@akunacapital.com
LinkedIn Profile matched
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Current company
Role
Senior Developer
Location
Altoona, Wisconsin, United States

Who is Matt Weber? Overview

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Quick answer

Matt Weber is listed as Senior Developer at Akuna Capital, based in Altoona, Wisconsin, United States. AeroLeads shows a work email signal at akunacapital.com and a matched LinkedIn profile for Matt Weber.

Matt Weber previously worked as FPGA and ASIC Design Consultant at Mweber Consulting Llc and Chief Architect at Alorium Technology. Matt Weber holds Ms, Electrical Engineering from University Of Minnesota.

Company email context

Email format at Akuna Capital

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{first}.{last}@akunacapital.com
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AeroLeads found 1 current-domain work email signal for Matt Weber. Compare company email patterns before reaching out.

Profile bio

About Matt Weber

Senior ASIC Architect and Logic Design Engineer with over 20 years of leading edge ASIC micro-architecture, design, verification, and consulting. Experience includes processor, networking, and storage applications. Successful project manager, team leader, technical sales, and primary customer interface for reusable ASIC IP products. Significant experience with CAD tools covering simulation, synthesis, static timing, equivalence checking, and formal functional verification.

Listed skills include Asic, Verilog, Logic Design, Static Timing Analysis, and 29 others.

Current workplace

Matt Weber's current company

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Akuna Capital
Akuna Capital
Senior Developer
AeroLeads page
8 roles

Matt Weber work experience

A career timeline built from the work history available for this profile.

Senior Developer

Current

Chicago, IL, US

Oct 2017 - Present

Fpga And Asic Design Consultant

Mweber Consulting Llc

Independent consultant delivering FPGA and ASIC design services in the following areas:- FPGA and ASIC design in System Verilog and VHDL- OpenCL FPGA Accelerators- SoC Architecture and Modeling- Reusable Interface IP- Hardware/Software Interfaces in embedded systems

Dec 2016 - Sep 2017

Chief Architect

Eau Claire, Wisconsin, US

Chief Architect and lead designer of Alorium's XLR8 product, a 2016 Wisconsin Innovation Awards Finalist- Developed FPGA based soft core microcontroller compatible with the Atmel ATmega328p- Conceived and delivered seamless integration of XLR8 with the Arduino IDE- Design of floating point, servo control, and other accelerator blocks, including associated.

Mar 2015 - Nov 2016

Principal Design Engineer

Eau Claire, WI, US

FPGA and ASIC design services and consulting primarily focused on FPGA accelation. Projects include the following:- Created custom Board Support Packages (BSP) for OpenCL implementations of software-defined networking (SDN) products using Altera OpenCL SDK and Arria 10 FPGAs- FPGA design for ultrasonic phased array transmit controller using Altera Cyclone.

Jun 2013 - Nov 2016

Ip Project Manager And Lead Designer

Bangalore, Karnataka, IN

Open-Silicon, IDT, Tundra Semiconductor, and Silicon Logic Engineering- Architect and team lead for industry’s first Hybrid Memory Cube (HMC) Host Controller IP- Lead designer and customer interface of 25-600Gbps Interlaken IP in 90nm to 22nm ASICs- Co-authored white paper promoting Interlaken standard- Designed SPI4.2 Phy IP, capable of 1Gbps data rates.

Mar 2003 - May 2013

Senior Logic Design Engineer

Bangalore, Karnataka, IN

Open-Silicon, IDT, Tundra Semiconductor, and Silicon Logic EngineeringASIC Design Services initially focused on synthesis, static timing analysis, and other CAD tools. Later focused on CPU and SoC architecture. Projects included the following:- Architected and Designed application specific 45nm VLIW processor for packet processing. Included developing.

Mar 2000 - May 2013

Staff Engineer

Ibm

Armonk, New York, NY, US

ASIC Design and Verification: SCSI and Fibre Channel Hard Disk Drive Controller ASICs- SCSI-U160M Controller ASIC Team Lead- SDRAM Memory Interface Design- Clock Design- ASIC Design Methodology including Synthesis, Timing, and Module Verification- Firmware Interface- Lab Debug

Apr 1995 - Mar 2000

Senior Associate Engineer

Ibm

Armonk, New York, NY, US

Test and Design Engineer for Flex Cable Assembly in Hard Disk Drive products.

Aug 1991 - Apr 1995
2 education records

Matt Weber education

Ms, Electrical Engineering

University Of Minnesota

Bs, Electrical Engineering

Michigan Technological University
FAQ

Frequently asked questions about Matt Weber

Quick answers generated from the profile data available on this page.

What company does Matt Weber work for?

Matt Weber works for Akuna Capital.

What is Matt Weber's role at Akuna Capital?

Matt Weber is listed as Senior Developer at Akuna Capital.

What is Matt Weber's email address?

AeroLeads has found 1 work email signal at @akunacapital.com for Matt Weber at Akuna Capital.

Where is Matt Weber based?

Matt Weber is based in Altoona, Wisconsin, United States while working with Akuna Capital.

What companies has Matt Weber worked for?

Matt Weber has worked for Akuna Capital, Mweber Consulting Llc, Alorium Technology, Superion Technology, and Open-Silicon.

How can I contact Matt Weber?

You can use AeroLeads to view verified contact signals for Matt Weber at Akuna Capital, including work email, phone, and LinkedIn data when available.

What schools did Matt Weber attend?

Matt Weber holds Ms, Electrical Engineering from University Of Minnesota.

What skills is Matt Weber known for?

Matt Weber is listed with skills including Asic, Verilog, Logic Design, Static Timing Analysis, Timing Closure, Soc, Logic Synthesis, and Semiconductors.

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