Matt Weber Email & Phone Number

Chicago, Il, Us

Independent consultant delivering FPGA and ASIC design services in the following areas:- FPGA and ASIC design in System Verilog and VHDL- OpenCL FPGA Accelerators- SoC Architecture and Modeling- Reusable Interface IP- Hardware/Software Interfaces in embedded systems

Eau Claire, Wisconsin, Us

Chief Architect and lead designer of Alorium's XLR8 product, a 2016 Wisconsin Innovation Awards Finalist- Developed FPGA based soft core microcontroller compatible with the Atmel ATmega328p- Conceived and delivered seamless integration of XLR8 with the Arduino IDE- Design of floating point, servo control, and other accelerator blocks, including associated Arduino libraries written in C, C++, and avr-gcc inline assembly code- Integrated python, Tkinter, C++, Quartus, avr-dude, and google drive to create an extremely low-cost, yet high quality manufacturing tester- Defined strategy and implementation details of XLR8 open source release

Eau Claire, Wi, Us

FPGA and ASIC design services and consulting primarily focused on FPGA accelation. Projects include the following:- Created custom Board Support Packages (BSP) for OpenCL implementations of software-defined networking (SDN) products using Altera OpenCL SDK and Arria 10 FPGAs- FPGA design for ultrasonic phased array transmit controller using Altera Cyclone V SOC with embedded dual ARM Cortex A9 processors - FPGA acceleration of C++ genome read alignment application using OpenCL on a Nallatech 385 PCIe accelerator card, including design and integration of custom verilog into the design- Design, Simulation, Clock Domain Crossing (CDC), Logical Equivalence Checking (LEC), and other audits for PCIe/XAUI/SRIO serdes subsystem in radiation tolerant FPGA design- Interlaken consulting, design, and lab debug in 22nm FPGA design

Bangalore, Karnataka, In

Open-Silicon, IDT, Tundra Semiconductor, and Silicon Logic Engineering- Architect and team lead for industry’s first Hybrid Memory Cube (HMC) Host Controller IP- Lead designer and customer interface of 25-600Gbps Interlaken IP in 90nm to 22nm ASICs- Co-authored white paper promoting Interlaken standard- Designed SPI4.2 Phy IP, capable of 1Gbps data rates, ported to thirteen different CMOS technologies in five different foundries, ranging from 180nm to 65nm- Designed SPI4.2 Phy IP testchip- Focused on Parameterized, Scalable, and Reusable designs- Developed IP revision control, CAD tool scripts and flow, and customer release process- Wrote and delivered specs, user guides, product briefs, and customer presentations- Trained India design team to support, maintain, and enhance Interlaken IP

Bangalore, Karnataka, In

Open-Silicon, IDT, Tundra Semiconductor, and Silicon Logic EngineeringASIC Design Services initially focused on synthesis, static timing analysis, and other CAD tools. Later focused on CPU and SoC architecture. Projects included the following:- Architected and Designed application specific 45nm VLIW processor for packet processing. Included developing custom instruction set, operand routing, and register file partitioning- Co-Architected Interlaken/Ethernet/XAUI Bridge/Switch/Aggregator chip in 40nm. Included evaluating clock rates, bus widths, and memory partitioning to ensure performance- Designed of three functional units of a Video Analytics Engine in 65nm- Reviewed Polymorphous Computing Architectures (PCA) and design processes- Architecture exploration of scaling PCA designs to different die sizes, performance goals, and ASIC technologies, including Rad Hard By Design (RHBD) techniques. Included modeling performance and chip size versus number and type of processing cores as well as modeling CPU pipeline changes to accommodate addition of floating point unit- Timing closure consulting for a very large multi-core processor design in 90nm- Performed parasitic extraction using Star-RCXT in 130nm technology- Provided architecture consulting for a Processor in Memory (PIM) design concept- Designed data capture, training, and automatic eye centering logic for 5Gbps serdes - Performed physical synthesis and technology translation of processor chips in 90nm- Performed rapid first pass translation of networking chips between ASIC technologies- Design Verification of functional units in cache coherent processor for NUMA architecture- Design for Test (DFT) and Static Timing Analysis (STA) of processor, memory, and cache controller chips for supercomputer design

Armonk, New York, Ny, Us

ASIC Design and Verification: SCSI and Fibre Channel Hard Disk Drive Controller ASICs- SCSI-U160M Controller ASIC Team Lead- SDRAM Memory Interface Design- Clock Design- ASIC Design Methodology including Synthesis, Timing, and Module Verification- Firmware Interface- Lab Debug

Armonk, New York, Ny, Us

Test and Design Engineer for Flex Cable Assembly in Hard Disk Drive products.

Ms, Electrical Engineering

Bs, Electrical Engineering