Michael Miller

Michael Miller Email and Phone Number

Networking IP Solutions Architect at Intel @ Altera
Saratoga, CA, US
Michael Miller's Location
Saratoga, California, United States, United States
About Michael Miller

Over 35 years of experience in product definition, creation, and applications work in the semiconductor and system businesses. His career has focused on innovating new products at the intersection of algorithms, software, and hardware in the areas of computing and networking. Through his career he has held engineering positions in software, hardware, logic design, system architecture, compilers, applications, OS porting, I/O drivers, board design, IC product definition, evangelizing and management. Most recently he has held CTO titles at IDT and MoSys.Career highlights:He personally conceived and created a new class of processor, Graph Memory Engine (GME), which he prototyped in C/Python and wrote a TCAM compiler in C to program it. GME can enable a wide range of classification applications from AI to database search and networking requiring high capacity and performance.Assembled and managed a cross functional team to productize the GME Stellar Mercury product composed of FPGA RTL, algorithm architects, software, firmware, and system engineers. Resulted in a 200Mb TCAM alternative product sufficient for 2 x 100GE firewall. Architecture will scale beyond 1Gb capacity and support for multi-terabit/s data rates.Architected a new class of very high access rate, high capacity, low latency SerDes attached monolithic memory resulting in 3 generations of product.Incubated a TCAM memory product line at IDT which was ultimately acquired by NetLogic for $90M in 2009.Conceived and patented the protocol which was ultimately defined the industry standard JTAG protocol that exists on most all silicon produced today.47+ US patents in system, software, hardware, protocols and chip architecture, cited by 1,500 patents from companies including Intel, IBM, Cisco, Micron, F5, and SanDisk. 14+ publications including IEEE, IEEE Mirco, HotChips, EDN, EE Times, MemCon, Embedded, OFC and Linley Tech Conferences.Specialties: Systems architecture, product architecture prototyping with C/Python, product definition, product verification, technical marketing and applications, managing cross functional software and hardware development, technology innovation, and IP acquisition

Michael Miller's Current Company Details
Altera

Altera

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Networking IP Solutions Architect at Intel
Saratoga, CA, US
Website:
altera.com.tr
Employees:
10
Michael Miller Work Experience Details
  • Altera
    Altera
    Saratoga, Ca, Us
  • Intel Corporation
    Networking Ip Solutions Architect
    Intel Corporation Aug 2022 - Present
    Santa Clara, California, Us
    Responsible for leading a team of hardware and software engineers developing networking search IP.
  • Mosys, Inc.
    Chief Technology Officer
    Mosys, Inc. May 2019 - Aug 2022
    San Jose, California, Us
    Responsible for raising the value of MoSys by defining, creating and promoting high level systems oriented products incorporating silicon, software and hardware in cutting edge markets such as Machine Learning, Edge Computing, Datacenter Acceleration, Genomics and Network Packet Processing.
  • Mosys, Inc.
    Vp Of Technology Innovation And Systems Applications
    Mosys, Inc. Jun 2009 - May 2019
    San Jose, California, Us
    Responsible for setting product and technology direction for MoSys as well as defining new Serial and Memory products. Focused on high speed 10 billion accesses per second 1 Gb memory ICs with 25Gbps serial interfaces for the networking and storage markets. The product incorporated 32 RISC cores to enable intelligent memory operations such as search and AI Convolutional Neural Network inferencing.
  • Micasys
    Owner/President
    Micasys Dec 2008 - Jun 2009
    Independent consultant to the semiconductor and related industries. Product direction planning, product defintion, system applications, and design consulting: ASIC or system design implementation and management, project management, design and marketing analysis, business intelligence application support.
  • Integrated Device Technology, Inc.
    Cto
    Integrated Device Technology, Inc. 2001 - Dec 2008
    San Jose, Ca, Us
    Served as the company's chief technical officer (CTO) and vice president of Systems Technology, responsible for systems-level and chip design technical issues. Worked with product lines in anticipating industry trends, evaluating new technologies and customer requirements, product definition and design of new products, and creating system-level reference designs. Responsible for multiple design centers and CAD group. Incubated new TCAM product line.
  • Integrated Device Technology, Inc.
    Vice President Of Engineering
    Integrated Device Technology, Inc. 1997 - 2001
    San Jose, Ca, Us
    Responsible for leading engineers in product definition and customer support in the areas of communications products such as switching and network interfaces. Team created reference designs and device drivers. Product responsibility included ATM PHY, SAR and switches.
  • Integrated Device Technology, Inc.
    Director Of Engineering
    Integrated Device Technology, Inc. 1989 - 1997
    San Jose, Ca, Us
    Lead team creating RISC software support tools, boards and subsystem modules. Support included BSD Unix port, "C" compliers, assembler, and debug monitors. Hardware designs included accelerator card and CPU modules.
  • Integrated Device Technology, Inc.
    Engineering Manager
    Integrated Device Technology, Inc. 1985 - 1989
    San Jose, Ca, Us
    Lead team performing product definition and applications engineering. Responsible for Bit Slice, Advanced Logic, and specialty memories.
  • Step Engineering
    Manager Of Software
    Step Engineering 1983 - 1985
    Managed software department developing microcode and debug tools. Job included applications code, OS ports and driver code for SCSI disk drive systems.
  • Nara Technologies
    Manager Of Software Development
    Nara Technologies 1982 - 1983
    Managed software team porting OS and developing 3D graphics rendering software.
  • Amd
    Applications And Product Definition Engineer
    Amd 1978 - 1982
    Santa Clara, California, Us
    Provided factory applications support and product definition of microcodable building block devices (2900 bitslice family). Performed logic design and verification functions. Conceived of and wrote an HDL compiler to describe and verify logic. Granted first serial diagnostic patent.

Michael Miller Skills

Semiconductors Asic Product Development Ic System Architecture Soc Hardware Intellectual Property Cross Functional Team Leadership Debugging Embedded Systems V&v Fpga Device Drivers Application Specific Integrated Circuits Functional Verification Microprocessors Eda System On A Chip Product Marketing Electronics Processors Mixed Signal Pcb Design Product Management Software Development Strategy Semiconductor Industry Technical Marketing Silicon Cmos

Michael Miller Education Details

  • California Polytechnic State University-San Luis Obispo
    California Polytechnic State University-San Luis Obispo
    Computer Architecture
  • San José State University
    San José State University
    Mathematics And Computer Science

Frequently Asked Questions about Michael Miller

What company does Michael Miller work for?

Michael Miller works for Altera

What is Michael Miller's role at the current company?

Michael Miller's current role is Networking IP Solutions Architect at Intel.

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What is Michael Miller's direct phone number?

Michael Miller's direct phone number is +140873*****

What schools did Michael Miller attend?

Michael Miller attended California Polytechnic State University-San Luis Obispo, San José State University.

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Michael Miller has skills like Semiconductors, Asic, Product Development, Ic, System Architecture, Soc, Hardware, Intellectual Property, Cross Functional Team Leadership, Debugging, Embedded Systems, V&v.

Who are Michael Miller's colleagues?

Michael Miller's colleagues are Ozer Pilge, Levent Ocaktan.

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