Malek Y. Al-Mallah, M.Sc. Email & Phone Number

Amman, Jo

Amman Governorate, Jordan

Job Responsibilities:- Working with a team of 30+ engineers (Locally) and 300+ engineers (globally) on developing the next generation of semiconductor foundational IPs.- Successfully participated in delivering several standard cell libraries with multiple architectures, such as high-speed (HS), high-density (HD), and ultra-high-density (UHD), on multiple VTs and channel lengths. These libraries include High-Performance Core (HPC) Kits, Power Optimization Kits (POK), Engineering… Show more Job Responsibilities:- Working with a team of 30+ engineers (Locally) and 300+ engineers (globally) on developing the next generation of semiconductor foundational IPs.- Successfully participated in delivering several standard cell libraries with multiple architectures, such as high-speed (HS), high-density (HD), and ultra-high-density (UHD), on multiple VTs and channel lengths. These libraries include High-Performance Core (HPC) Kits, Power Optimization Kits (POK), Engineering Change Order (ECO) Kits, and other requirements-optimized kits.- Developing both the transistor-level circuit and layout for High-performance flip flops, DICE flip flops, Retention flip flops, Synchronizers, Clock Gaters, level Shifters, and other complex functions on state-of-the-art CMOS technologies. - Multibit cells design and area, power, CK capacitance benefit analysis.- Carrying the design from DRC, ERC, LVS, and DFM verification using ICV and Calibre tools, throughout Power Performance Area (PPA) trade-offs and optimization, to Robustness check on all PVTs using HSpice.- Optimizing the design by considering Layout-Dependent Effects (LDE) and Process Variation.- Performing advanced analysis on designs, such as charge sharing, race margin, electro-migration, Monte Carlo, sigma, safe operating area, power sequencing, and leakage analysis.- Developing numerical techniques to estimate Synchronizers' MTBF.- Deliver several training sessions on high-performance flip-flop architectures and metastability analysis.- All designs have been done on the following CMOS technologies: MBCFET: 3nm. FinFET: 4nm, 8nm, and 12nm. SOI: 20nm, 28nm, and 36nm. Planer-Bulk: 40nm. Show less

Amman Governorate, Jordan

- Published two papers in IEEE conferences:1. Malek Y. Al-Mallah, Zaid I. Saleh and Yanal S. Faouri "Two Feed Reconfigurable Microstrip Patch Antenna for Polarization Diversity." IEEE JEEIT 2019, Amman, Jordan.2. Zaid I. Saleh, Malek Y. Al-Mallah and Yanal S. Faouri "Polarization Reconfigurable Microstrip Slotted Antenna with Two Opposite Feeds." IEEE GPECOM 2019, Cappadocia, Nevsehir, Turkey.- Published a paper in Journal of Critical Reviews:1. YS Faouri, NM… Show more - Published two papers in IEEE conferences:1. Malek Y. Al-Mallah, Zaid I. Saleh and Yanal S. Faouri "Two Feed Reconfigurable Microstrip Patch Antenna for Polarization Diversity." IEEE JEEIT 2019, Amman, Jordan.2. Zaid I. Saleh, Malek Y. Al-Mallah and Yanal S. Faouri "Polarization Reconfigurable Microstrip Slotted Antenna with Two Opposite Feeds." IEEE GPECOM 2019, Cappadocia, Nevsehir, Turkey.- Published a paper in Journal of Critical Reviews:1. YS Faouri, NM Awad, MY Al-Mallah, ZI Saleh "Frequency Reconfigurable Antenna with Two Orthogonal Microstrip Feeds" Journal of Critical Reviews, 2020.- See Dr Yanal Certification below. Show less

Amman Governorate, Jordan

Amman, Jordan

I served as a member of the preparatory committee for the Arab Regional Relations Symposium.

M.Sc., Electrical Engineering, 96.2% (Ranked 1St)

Class valedictorian

B.Sc., Electrical, Electronics And Communications Engineering, Very Good