Ruben R. Email & Phone Number

Sunnyvale, California, US

• Trained in Artificial Intelligence and Machine Language. Trained and hands on in Python coding. ASIC Physical Design Consulting engineer, self-motivated electrical engineer (MSEE) with over 23+ years of diverse.
• ASIC Design Methodology Development* ASIC Power Methodology

Milpitas, California, US

• Consulting at ASTERA LABS,INC. Sunnyvale, California
• Tools: ICC2, ICV, VUE, Sed/AWK, TcL, Makefile
• Process: TSMC **CONFIDENTIAL ***
• Std Cell Library: TSMC
• Completed work: Urgent, right before tapeout, DRC, LVS, ANT verification, repair

Santa Clara, California, US

Continue working at Intel Corp. at Santa Clara as an employee of Esencia Technologies, Inc. The work includes programming in Tcl to do full chip integration. Using ICC2 in the process on the hierarchical full chip integration. Using Perforce for versioning control. Developing scripts to allow for full chip intergration. Using 10nm INTEL ASIC and custom.

Santa Clara, California, US

Hired to consult on-site for Intelliswift as a Senior Physical Designer. This included 10nm technology, place and route, using INTEL design flow, EDA tools by Synopsys (for example ICC2), project management and floorplanning exploration and timing convergence and deliver a floorplan that includes 4 large each 2 million gates blocks. Project also included.

San Diego, CA, US

Contracted to do synthesis/floorplanning/place and route/cts/static timing analysis/extraction/LVS/DRC/DFM. Challenge, to improve performance of a taped out design. Technology is 180nm and EDA tools are Cadence/Synopsys/Mentor Graphics.

San Jose, CA - California, US

Contracted to take a soft IP and harden it by taking the synthesized netlist through place and route and qualifying it using timing reports and physical verification. Automated the design and tools flow by scripting the environment. The EDA tools are Cadence Innovus and the technology is TSMC 16nm using the Avago 16nm standard cell library. The harden IP.

Palo Alto, California, US

Contracted to do full chip static timing analsys and physical design. Deliverables are scripts to help analyze timing relation issues and solutions to timing violations. I worked with other timing engineers to help converge on timing at the full chip. Analyzed timing reports from Cadence Tempes and Place and route scripts from ATOP Technologies.

Parsippany, NJ, US

Write technical collaterals: datasheets, app notes, white papers, product briefs, technical product training materials to help train sales and marketing team and establish quicker adoption of PNY SSD products. Work with content experts to define gaps in existing content, and develop appropriate content solutions addressing the needs. Work with cross.

Santa Clara, California, US

• Technical member of the SERDES1 IP design team.
• Using process down to 20nm.
• Using Synopsys ICC & Primetime, Mentor Graphics Calibre, and Cadence SOC Encounter.
• Using advance design automation internal tools. Also, using Perforce and FlowTracer for design automation.
• Application of circuit design or logic optimization to converge on timing.
• Responsible for physical design implementation of complex SoCs.

Santa Clara, California, US

Using Synopsys ICC & Primetime, Mentor Graphics Calibre, and Cadence SOC Encounter. Using advance design automation internal tools. Also, using Perforce and FlowTracer for design automation. Using process down to 28nm. Application of circuit design or logic optimization to converge on timing. Responsible for physical design implementation of complex SoCs..

Santa Clara, CA, US

Using Synopsys ICC & Primetime, MAGMA Talus, Mentor Graphics Calibre, and Cadence SOC Encounter. Using process down to 40nm. Responsible for physical design implementation of complex SoCs. Participating in physical design methodologies and flow automation. Floorplan, place&route, signal integrity avoidance/fixing, power/clock distribution, timing closure.

Responsible for identifying, qualifying and closing IP sales opportunities for ChipStart, LLC in Northern California (Silicon Valley). Achieve revenue targets. Manage relationships at management & operational levels with customers and partners. Sales forecasting with high degree of accuracy. Understand customer needs/expectations and decision making.

Strategic Consulting, including business plan & sales strategy development.

• Responsible for the development of strategic account penetration plans and annual bookings objectives for IP products.
• Responsible for developing business proposals and negotiating large value opportunities define and maintain detailed account development plan for IP and design services based opportunities. These plans should include.
• Included weekly reports on account progress, develop and own strategic and tactical relationships at management, engineering and marketing levels; gain understanding of informal decision making organization.
• Work with sales team to negotiate and close contracts for IP based products.
• Represent partner to customer and provide feedback to design partners, engineering, marketing and management regarding partner technical and business requirements.
• Facilitate contract deliverables to partners and manage issues that arise Identify and capture competitive landscape, trends, unit and ASP projections, acquisition activities and other relevant partner information.

US

• Responsible for the development of strategic account penetration plans and annual bookings objectives for IP products.
• Responsible for developing business proposals and negotiating large value opportunities define and maintain detailed account development plan for IP and design services based opportunities. These plans should include.
• Included weekly reports on account progress, develop and own strategic and tactical relationships at management, engineering and marketing levels; gain understanding of informal decision making organization.
• Work with sales team to negotiate and close contracts for IP based products.
• Represent partner to customer and provide feedback to design partners, engineering, marketing and management regarding partner technical and business requirements.
• Facilitate contract deliverables to partners and manage issues that arise Identify and capture competitive landscape, trends, unit and ASP projections, acquisition activities and other relevant partner information.

Recommended and experience is developing designs flows from synthesis to tape-out GDS in Synopsys, Cadence and MAGMA using 65nm process nodes and higher.Including the proven ability to manage projects, interview, qualify and hire design engineers.

* ASIC Physical Design from netlist to GDSII.* ASIC Design Methodology Development.* Tools flow development and evaluation.* Worked with Sales in new development deals for new business opportunities.* Developed brand strategies with Sales. * Strategic Consulting, including business plan & sales strategy development for start-ups.

Sunnyvale, California, US

Support customers using Astro/Physical Compiler/other backend tools from SynopsysSupport R&D in tool testing and developementSupport Coprorate Application Engineers.Develop test plansDevelop product featuresDevelop tools flows and design methodologies

San Jose, California, US

Physical design using Cadence Virtuoso, CELL3, Preview, taped out designs using Silicon Ensemble, LEF&DEF, SED&AWK scripting, Floorplanning, Place&Route, using 0.35um process, design methodology development and assessment, EDA support for Silicon Ensemble and DRACULA.

Armonk, New York, NY, US

* Touch screen research & product development.* Worked on IBM's leading edge submicron technology in custom physical design & methodology.* Worked on several IBM chips and products: PowerPC 630 chip, TouchSelect, 4055 Infowindows, 8516 Touchscreen, and the Advanced Technology Classrooms, & systems on a chip(ASIC).* Worked with IBM's leading edge submicron.

Msee, Control Systems

Bsee With Honors, Electrical Engineering