Ruben R.

Ruben R. Email and Phone Number

Principal ASIC Physical Design Engineer Consultant at Athena Cloud Engineers, Inc. @ Athena Cloud Engineers, LLC
Ruben R.'s Location
San Francisco Bay Area, United States, United States
Ruben R.'s Contact Details
About Ruben R.

OPEN FOR WORK. Completed a two contract. Process 3nm. RTL2GDS. ASIC Power/Physical/Methodology Design Engineer. Trained in Artificial Intelligence and Machine Language. Trained and hands on in Python coding. Experienced in ASIC Physical Design Consulting engineer, self-motivated electrical engineer (MSEE) with over 23 years of diverse experience in electrical engineering, IP sales, business management, project management, IC chip physical design, Engineering Design Automation (EDA) software development, EDA tool integration, ASIC design methodology, physical sciences research. Over 10 taped out designs using leading edge technology from IBM and TSMC using market leader EDA tools such as IBM, Cadence, Synopsys and MAGMA. Active consultant ASIC physical design and methodology development and practical in-depth knowledge of the leading EDA physical design tools from Cadence, MAGMA and Synopsys and associated tools flow.Interested in working with bleeding edge process technology, physical design and methodology development and related technical business, marketing and sales managing.Specialties: • Artificial Intelligence and Machine Language*. Python, Cornell Certification (complete Jan 2024)* AI & ML, Cornell Certification (complete June 2024)*. ASIC Physical Design• ASIC Design Methodology Development

Ruben R.'s Current Company Details
Athena Cloud Engineers, LLC

Athena Cloud Engineers, Llc

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Principal ASIC Physical Design Engineer Consultant at Athena Cloud Engineers, Inc.
Ruben R. Work Experience Details
  • Athena Cloud Engineers, Llc
    Principal Asic Physical Design Engineer Consultant
    Athena Cloud Engineers, Llc Mar 2019 - Present
    Sunnyvale, California, Us
    Trained in Artificial Intelligence and Machine Language. Trained and hands on in Python coding. ASIC Physical Design Consulting engineer, self-motivated electrical engineer (MSEE) with over 23+ years of diverse experience in electrical engineering, IP sales, business management, project management, IC chip physical design, Engineering Design Automation (EDA) software development, EDA tool integration, ASIC design methodology, physical sciences research. Over 10+ taped out designs using leading edge technology from IBM and TSMC using market leader EDA tools such as IBM, Cadence, Synopsys and MAGMA. Active consultant ASIC physical design and methodology development and practical in-depth knowledge of the leading EDA physical design tools from Cadence, MAGMA and Synopsys and associated tools flow. End clients: Meta, Synopsys, Broadcom, GOOGLE, Astera Labs, INTEL, etc.Interested in working with bleeding edge process technology, physical design and methodology development and related technical business, marketing and sales managing.Specialties: * Artificial Intelligence and Machine Language* Python Programming, Cornell Certification* APPLIED MACHINE LEARNING AND AI, Cornell Certification (WORKING)* ASIC Physical Design• ASIC Design Methodology Development* ASIC Power Methodology
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  • Self-Employed
    Principal Consultant
    Self-Employed May 2018 - Present
  • Mobiveil Inc.
    Asic Physical Design Engineer
    Mobiveil Inc. Mar 2019 - Mar 2019
    Milpitas, California, Us
    Consulting at ASTERA LABS,INC. Sunnyvale, California• Tools: ICC2, ICV, VUE, Sed/AWK, TcL, Makefile• Process: TSMC **CONFIDENTIAL ***• Std Cell Library: TSMC• Completed work: Urgent, right before tapeout, DRC, LVS, ANT verification, repair
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  • Intel Corporation
    Design Automation Engineer Consultant
    Intel Corporation Apr 2017 - May 2018
    Santa Clara, California, Us
    Continue working at Intel Corp. at Santa Clara as an employee of Esencia Technologies, Inc.
 The work includes programming in Tcl to do full chip integration. Using ICC2 in the process on the hierarchical full chip integration. Using Perforce for versioning control. Developing scripts to allow for full chip intergration. Using 10nm INTEL ASIC and custom libraries. All work is being done at the top level. The work includes doing DRC checking using SYNOPSYS icv and icwbev. I cannot discuss the detail, but all is very exciting.
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  • Intel Corporation
    Asic Senior Physical Design Engineer Consultant
    Intel Corporation Aug 2016 - Feb 2017
    Santa Clara, California, Us
    Hired to consult on-site for Intelliswift as a Senior Physical Designer. This included 10nm technology, place and route, using INTEL design flow, EDA tools by Synopsys (for example ICC2), project management and floorplanning exploration and timing convergence and deliver a floorplan that includes 4 large each 2 million gates blocks. Project also included, documentation of tasks, status reports and meetings.
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  • Qualcomm
    Asic Physical Designer Consultant
    Qualcomm Jun 2016 - Aug 2016
    San Diego, Ca, Us
    Contracted to do synthesis/floorplanning/place and route/cts/static timing analysis/extraction/LVS/DRC/DFM. Challenge, to improve performance of a taped out design. Technology is 180nm and EDA tools are Cadence/Synopsys/Mentor Graphics.
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  • Eximius Design
    Senior Asic Physical Design Engineer Consultant
    Eximius Design Feb 2016 - May 2016
    San Jose, Ca - California, Us
    Contracted to take a soft IP and harden it by taking the synthesized netlist through place and route and qualifying it using timing reports and physical verification. Automated the design and tools flow by scripting the environment. The EDA tools are Cadence Innovus and the technology is TSMC 16nm using the Avago 16nm standard cell library. The harden IP is over 20 million gates.
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  • Broadcom
    Asic Physical Designer (Consultant)
    Broadcom Nov 2015 - Jan 2016
    Palo Alto, California, Us
    Contracted to do full chip static timing analsys and physical design. Deliverables are scripts to help analyze timing relation issues and solutions to timing violations. I worked with other timing engineers to help converge on timing at the full chip. Analyzed timing reports from Cadence Tempes and Place and route scripts from ATOP Technologies.
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  • Pny Technologies
    Technical Marketing Engineer Consultant
    Pny Technologies Oct 2014 - Sep 2015
    Parsippany, Nj, Us
    Write technical collaterals: datasheets, app notes, white papers, product briefs, technical product training materials to help train sales and marketing team and establish quicker adoption of PNY SSD products. Work with content experts to define gaps in existing content, and develop appropriate content solutions addressing the needs. Work with cross functional teams to characterize PNY SSD, performance benchmark and generate collateral to help competitive positioning of the product and to communicate the value. Manage and help drive third party reviews and validations of competitive technical data including at application and synthetic test level. Support Marketing and Business Development efforts to broaden the customer base, support design win-design-in opportunities. Develop demos, proof points etc. for roadshows to establish product goodness and showcase user perceivable value additions. Lead discussion panels at conferences and industry group events and/or product shows.
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  • Amd
    Mts (Member Of Technical Staff) Design Engineer
    Amd Apr 2013 - Jun 2014
    Santa Clara, California, Us
    • Technical member of the SERDES1 IP design team. • Using process down to 20nm.• Using Synopsys ICC & Primetime, Mentor Graphics Calibre, and Cadence SOC Encounter.• Using advance design automation internal tools. Also, using Perforce and FlowTracer for design automation.• Application of circuit design or logic optimization to converge on timing.• Responsible for physical design implementation of complex SoCs.• Participating in physical design methodologies and flow automation.• Floorplan, place&route, signal integrity avoidance/fixing, power/clock distribution, timing closure - timing, power, clock and noise analysis and DRC/LVS.Timing closure. clock/power distribution & analysis, signal integrity, and DFM.• Writing scripts in SED, AWK, Python, Tcl and Perl.
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  • Amd
    Asic Physical Design Engineer Consultant
    Amd Sep 2011 - Apr 2013
    Santa Clara, California, Us
    Using Synopsys ICC & Primetime, Mentor Graphics Calibre, and Cadence SOC Encounter. Using advance design automation internal tools. Also, using Perforce and FlowTracer for design automation. Using process down to 28nm. Application of circuit design or logic optimization to converge on timing. Responsible for physical design implementation of complex SoCs. Participating in physical design methodologies and flow automation. Floorplan, place&route, signal integrity avoidance/fixing, power/clock distribution, timing closure - timing, power, clock and noise analysis and DRC/LVS.Timing closure. clock/power distribution & analysis, signal integrity, and DFM. Writing scripts in SED, AWK, Tcl and Perl.
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  • Synapse Design Automation Inc.
    Senior Physical Desgn Engineer Consultant
    Synapse Design Automation Inc. Jun 2011 - Jul 2011
    Santa Clara, Ca, Us
    Using Synopsys ICC & Primetime, MAGMA Talus, Mentor Graphics Calibre, and Cadence SOC Encounter. Using process down to 40nm. Responsible for physical design implementation of complex SoCs. Participating in physical design methodologies and flow automation. Floorplan, place&route, signal integrity avoidance/fixing, power/clock distribution, timing closure - timing, power, clock and noise analysis and DRC/LVS.Timing closure. clock/power distribution & analysis, signal integrity, and DFM. Writing scripts in SED, AWK, Tcl and Perl.
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  • Chipstart
    Business Manager Consultant
    Chipstart Mar 2011 - Apr 2011
    Responsible for identifying, qualifying and closing IP sales opportunities for ChipStart, LLC in Northern California (Silicon Valley). Achieve revenue targets. Manage relationships at management & operational levels with customers and partners. Sales forecasting with high degree of accuracy. Understand customer needs/expectations and decision making process. Identify and qualify projects. Build accurate pipeline to manage priorities and provide forecast. Define account plans and execute them through effective planning of resources. Present proposals, manage negotiations and close the sales. Gain strategic information about customers and the industry to help anticipate market trends. Participation in trade shows, client conferences, industry events, etc. Partner with and develop key relationships with Regional head (management), Business Team (product marketing, product specialist), and Professional Services (pre and post sales support). Build and leverage relationships with existing and potential customers and partners. Use of CRM tools. Track and provide feedback on quality of leads.
  • Ruben Reyes
    Engineering/Sales/Business Development Consultant
    Ruben Reyes Feb 2011 - Mar 2011
    Strategic Consulting, including business plan & sales strategy development.
  • Trivium Tech Force Corporation
    Principal Engineer And Founder
    Trivium Tech Force Corporation Feb 2010 - Jan 2011
    • Responsible for the development of strategic account penetration plans and annual bookings objectives for IP products.• Responsible for developing business proposals and negotiating large value opportunities define and maintain detailed account development plan for IP and design services based opportunities. These plans should include sales goals, strategic target goals and plans to grow partner’s commitment.• Included weekly reports on account progress, develop and own strategic and tactical relationships at management, engineering and marketing levels; gain understanding of informal decision making organization.• Work with sales team to negotiate and close contracts for IP based products.• Represent partner to customer and provide feedback to design partners, engineering, marketing and management regarding partner technical and business requirements.• Facilitate contract deliverables to partners and manage issues that arise Identify and capture competitive landscape, trends, unit and ASP projections, acquisition activities and other relevant partner information.• Gain working knowledge of partner technical and business strengths, target markets
  • Global Trivium Corporation
    Principal Engineer And Founder
    Global Trivium Corporation Mar 2009 - Feb 2010
    Us
    • Responsible for the development of strategic account penetration plans and annual bookings objectives for IP products.• Responsible for developing business proposals and negotiating large value opportunities define and maintain detailed account development plan for IP and design services based opportunities. These plans should include sales goals, strategic target goals and plans to grow partner’s commitment.• Included weekly reports on account progress, develop and own strategic and tactical relationships at management, engineering and marketing levels; gain understanding of informal decision making organization.• Work with sales team to negotiate and close contracts for IP based products.• Represent partner to customer and provide feedback to design partners, engineering, marketing and management regarding partner technical and business requirements.• Facilitate contract deliverables to partners and manage issues that arise Identify and capture competitive landscape, trends, unit and ASP projections, acquisition activities and other relevant partner information.• Gain working knowledge of partner technical and business strengths, target markets
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  • Ruben Reyes
    Ic Physical Design Engineer & Project Management Consultant
    Ruben Reyes Jul 2008 - Mar 2009
    Recommended and experience is developing designs flows from synthesis to tape-out GDS in Synopsys, Cadence and MAGMA using 65nm process nodes and higher.Including the proven ability to manage projects, interview, qualify and hire design engineers.
  • Qthink
    Senior Design Engineer
    Qthink Oct 2004 - Jul 2008
    * ASIC Physical Design from netlist to GDSII.* ASIC Design Methodology Development.* Tools flow development and evaluation.* Worked with Sales in new development deals for new business opportunities.* Developed brand strategies with Sales. * Strategic Consulting, including business plan & sales strategy development for start-ups.
  • Synopsys
    Staff Corporate Applicaton Engineer
    Synopsys Sep 1998 - Dec 2003
    Sunnyvale, California, Us
    Support customers using Astro/Physical Compiler/other backend tools from SynopsysSupport R&D in tool testing and developementSupport Coprorate Application Engineers.Develop test plansDevelop product featuresDevelop tools flows and design methodologies
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  • Cadence Design Systems
    Senior Design Consultant
    Cadence Design Systems Feb 1993 - Oct 1998
    San Jose, California, Us
    Physical design using Cadence Virtuoso, CELL3, Preview, taped out designs using Silicon Ensemble, LEF&DEF, SED&AWK scripting, Floorplanning, Place&Route, using 0.35um process, design methodology development and assessment, EDA support for Silicon Ensemble and DRACULA.
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  • Ibm Thomas J. Watson Research Center
    Engineer
    Ibm Thomas J. Watson Research Center Dec 1982 - Jan 1993
    Armonk, New York, Ny, Us
    * Touch screen research & product development.* Worked on IBM's leading edge submicron technology in custom physical design & methodology.* Worked on several IBM chips and products: PowerPC 630 chip, TouchSelect, 4055 Infowindows, 8516 Touchscreen, and the Advanced Technology Classrooms, & systems on a chip(ASIC).* Worked with IBM's leading edge submicron technology (cmos5x and cmos7) in custom physical design. As well as setting up a design methodology for measuring performance when doing custom physical design.* Designed a custom 64-bit register, using IBM technology, hard block for a CPU chip for the datapath. Using cmos5x, 0.25micron IBM technology. Physical design and verification (IBM Niagara and Cadence Dracula).* Created and lead in establishing one way of doing remote verification for his custom physical design team.* I took an intensive CMOS design course by IBM and instructors from Columbia, Cornell, and MIT.* Co-authored several IBM white papers.
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Ruben R. Education Details

  • New York University - Polytechnic School Of Engineering
    New York University - Polytechnic School Of Engineering
    Control Systems
  • Pratt Institute
    Pratt Institute
    Electrical Engineering

Frequently Asked Questions about Ruben R.

What company does Ruben R. work for?

Ruben R. works for Athena Cloud Engineers, Llc

What is Ruben R.'s role at the current company?

Ruben R.'s current role is Principal ASIC Physical Design Engineer Consultant at Athena Cloud Engineers, Inc..

What is Ruben R.'s email address?

Ruben R.'s email address is of****@****yes.com

What is Ruben R.'s direct phone number?

Ruben R.'s direct phone number is +140864*****

What schools did Ruben R. attend?

Ruben R. attended New York University - Polytechnic School Of Engineering, Pratt Institute.

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