Nagesh Loke Email and Phone Number
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Meta - building world class AI/ML chip solutions - Responsible for all technical aspects in DV, uArch performance correlation - Work closely with perf/modeling, emulation, SW/FW, bare-metal teams to land high-class silicon - Drive innovation by introducing multiple new techniques, debug improvements - Engineering manager - responsible for personal development, growth, 1:1, hiring, performance cyclesAWS - Delivered multiple versions of Trainium (AI/ML chip solution)- Responsible for DV & emulation for Trainium delivering industry leading deep learning models in EC2- Hands-on technical lead and team manager- Pre-Si & Arch validation (Emulation) technical lead responsible for full system bring up, stress and driving system performance to spec- Technical lead for simulation, emulation, formal verification and design automation teams in a fast paced, cutting edge environmentARM & Qualcomm- Managed a multi-level team of engineers; Responsible for career guidance, happiness, hiring, planning- Memory Subsystem Lead (Load-Store, L2 and MMU) - focusing on technical strategy for verification- Leading Machine Learning/Data Science application for CPU Verification across ARM- Chair for internal Verification Quality initiatives- Verification Lead for ARM Cortex-A class cores; leading all aspects of verification (Unit level, Core, TOP, AVS/DVS, memory subsystem, Validation)- Validated AMBA 5 CHI; Contributed to the successful delivery of CCN-504 - Cache Coherent Network products- Expertise in multi-cluster cache coherence verification, CPU uArch- Unit-level, core/cluster level and full-chip/SoC verification for DSP cores, Snapdragon SoCs and PHY designs- UVM, Constrained-random & coverage driven verification- Assertion based verification
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Asic Engineering Manager/Tech Lead, Design VerificationMeta Dec 2022 - PresentMenlo Park, Ca, Us
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Design Verificatiion Manager, Ml Soc Arch Validation/Emulation Technical LeadAmazon Web Services (Aws) Apr 2020 - Dec 2022Seattle, Wa, Us- Bring up, stress test and deliver on performance on emulation platform to spec for the next generation ML SoC; run HW focused stress tests and interface w/ SW team to ensure successful performance of SW workloads and utilization of HW- Responsible for simulation, emulation, formal verification, design automation & verification methodology- Plan, execute and lead a strong team of engineers to successful functional closure and various milestones leading to RTL freeze and successful TO- Responsible for fabric deadlock verification (planning and execution), various aspects of chip functionality- DV manager (1:1s, hiring, team performance/assessments, vendor relation)- Delivered on fully functional A0 silicon for Trainium SoC (best performing deep learning chip on the cloud); https://aws.amazon.com/machine-learning/trainium/ -
Sr. Principal EngineerArm Nov 2011 - Apr 2020Cambridge, Cambs, GbVerification Lead for ARM V8 CPU Cores in AustinCortex A77https://www.anandtech.com/show/14384/arm-announces-cortexa77-cpu-ipCortex A72http://www.arm.com/products/processors/cortex-a/cortex-a72-processor.phpCortex A57http://www.arm.com/products/processors/cortex-a/cortex-a57-processor.phpAMBA 5 CHIhttp://www.arm.com/about/newsroom/arm-announces-amba-5-chi-specification-to-enable-high-performance-highly-scalable-system-on-chip.phpCCN-504http://www.arm.com/about/newsroom/arm-announces-new-high-performance-system-ip-to-address-demand-for-energy-efficient-many-core.php -
Staff Verification EngineerQualcomm Mar 2006 - Nov 2011San Diego, Ca, Us- Responsible for verifying the control unit of a microprocessor. Involved in all aspects of verification - planning, task assignment, constrained-random stimulus, checkers, integration with the core, functional coverage implementation and closure. Designed the unit for easy core level migration. Used System Verilog/OVM & assertions.- Developed a comprehensive memory checker that verifies all the caches and memories in the core against the reference model. This checker has comprehensive understanding of various levels of caches, memories, keeps track of snoop activity etc.- Verified a DSP CPU at the core and SoC level. This includes leading a team of 6 engineers in three different time zones, schedule tracking, delivery responsibility- VMM to OVM migration of SV code- Responsible for creating a template for ViP for PHY designs -
Mts Verification EngineerSigmatel Inc Jan 2005 - Mar 2006- Developed complete Vera based testbench architecture from scratch for a brand new product. This included developing reusable components for stimulus generation, checking, reporting and general utilities (drivers, monitors, checkers, generators, functional coverage) - Verified an audio codec (both block-level and reuse at System-level). Blocks included industry standard I2S in various flavors.- Introduced new verification techniques (Vera RVM & OOP) and assertion-based verification.- Created & maintained build, simulation and regression infrastructure (using OO Perl)- Developed a web-based scheme to monitor regressions. This was done using Apache and running Perl/CGI scripts on the backend. Integrated functional & code coverage reports into this scheme
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Sr. Verification Methodology EngineerFreescale Semiconductor Jun 1998 - Dec 2004Austin, Texas, Us- Responsible for development, support and release of internal RVM like base classes across various product groups for entire Freescale. - Responsible for advocating formal & semi-formal verification techniques in verification.- Responsible for evaluating vendor tools for formal verification. - Involved in the development and deployment of System Verilog assertions across the company.- Helped with training modules intended to make users familiar with the usage and advantages of assertions.- Worked on a pilot project for a processor core to help drive the usage of assertion-based verification techniques – specifically property/model checking- Responsible for developing, supporting and releasing an RTL to custom gate netlist generator for internal use across the company.- Responsible for developing a verilog compiler, parser.- Responsible for developing and maintaining a web-based regression flow that helped
Nagesh Loke Skills
Nagesh Loke Education Details
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Texas A&M UniversityElectrical Engineering -
Jawaharlal Nehru Technological UniversityElectronics & Communication Engineering
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Little Flower Junior CollegePhysics & Chemistry
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All Saints' High School
Frequently Asked Questions about Nagesh Loke
What company does Nagesh Loke work for?
Nagesh Loke works for Meta
What is Nagesh Loke's role at the current company?
Nagesh Loke's current role is Building AI/ML chips & solutions. ASIC Engineering Manager, DV Tech Lead..
What is Nagesh Loke's email address?
Nagesh Loke's email address is na****@****arm.com
What is Nagesh Loke's direct phone number?
Nagesh Loke's direct phone number is 1-512-257*****
What schools did Nagesh Loke attend?
Nagesh Loke attended Texas A&m University, Jawaharlal Nehru Technological University, Little Flower Junior College, All Saints' High School.
What are some of Nagesh Loke's interests?
Nagesh Loke has interest in Science And Technology, Children, Education.
What skills is Nagesh Loke known for?
Nagesh Loke has skills like Systemverilog, Verilog, Functional Verification, Soc, Simulations, Processors, Asic, Debugging, Perl, Microprocessors, Formal Verification, Digital Signal Processors.
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