Naishad Parikh Email & Phone Number

Mumbai, Mh, In

Bengaluru, Karnataka, India

Bengaluru Area, India

Bengaluru Area, India

Bengaluru Area, India

Bengaluru Area, India

Managing a team of STA engineers for 20nm, 16FinFet and 14nm Testchips for TSMC and Samsung foundries and for Qualcomm Multi-Foundry ProductsLed Timing team for 5 Testchips and 2 QMD designsManaging Constraints Validation and Delivery for PD implementation Collaborating with Design team to understand Clock architecture and Interface timing requirement to help PD team for implementationDriving block owners for timing convergenceDriving validation and deployment of Synopsys Primetime HyperScale technology for 14nm Testchip and thereby leveraging it for other designs across teamsPost-Silicon debug, FIB suggestion on 1st 20nm Testchip and help de-risk 1st 20nm Product tape-out

Bangalore

Key Deliverable:Represented Design team in Debug of Audio Noise for customers like Barnes & Noble and PMC- Part of debug team to resolve critical Audio Noise issue seen between OMAP4 and Audio Codecs at system level- Recommended Board level solution to overcome the noise issue.System timing budgets generation for OMAP5 and OMAP6 SoCs (28nm)- Package/PCB Signal Integrity analysis for system hardware interfaces- Create System level budgets for Audio interfaces like McBSP, McASP, DMIC, PDM and Slimbus, Storage interfaces like SDCARD, eMMC and Debug interfaces.IO development for OMAP6430 SoC (28nm)- Developed CORE-IO isolation strategy to reduce IO-STA runtime- Developed strategies to cut down the number of IO-STA modes by 50%- Developed an isolated Multi Mode-Multi Corner Scenario for IO modes to expedite IO timing convergence

Key Deliverable:I/O Timing Closure for OMAP4 SoC (45nm)- High speed Interfaces like DDR, HSIC, GPMC, USB and MMC and other peripherals like MCBSP, MCSPI- Piloted in creating collaborative methodology of validating IO timing in Gate Simulations.Test Mode Closure and Merged-Mode SDC generation for OMAP4430 SoC (45nm)- Created robust constraints for Transition Fault Test mode in collaboration with France and India DFT teams.- Collaborated with DFT team in creating and deploying SDC-based flow to generate At-speed patterns in an effort to improve test coverage.- Spearheaded robust QC process for layout constraints. Synthesis, I/O timing, Test Mode (TFT) Closure and mentoring IP activities for OMAP3 SoC (45nm)- Transitioned complete bottom-up synthesis setup consisting of over 30 soft + hard IPs from its parent device OMAP3 SoC (65nm)- Deployed DC-Topo feature for the first time at SoC level.Transitioned and validated IO constraints for protocols like MDDR, USB, MMC, MCBSP, SPI, Camera, Display, and so on.- Created an SDC-based flow to help DFT team meeting at-speed coverage goals.IO-Ring Creation, IR-Analysis, Clock tree synthesis, PM Checks, STA for Locosto Single Chip Solution (65nm)- Collaborated with in-house I/O ring creation flow group in creating a customized methodology to handle multi-bonded IO ring. - Building power-grid and doing IR drop analysis.- Building custom and robust clock tree to achieve skew and power goals.- Enabling Cadence's Conformal Low Power checks successfully for the first time at SoC level.

Placement, Clocks and STA for c55x DSP and ARM9 cores (65nm and 90nm)Constraints coding and timing closure of high speed and critical DARAM memories. Placement of performance critical ALU, MAC blocks of DSP.