Research And Development Engineer
Hsinchu County/City, Taiwan
During my time at Synopsys, I was an R&D engineer working on the debug platform, Verdi. Hardware engineers would use Verdi to debug their Verilog/VHDL designs. The most frequently used features were nTrace (used to trace through the source code), nWave (used to show the simulated waveforms of the design) and nSchema (shows the schematic view of the design). Our group was developing an advanced feature called Temporal Flow View, or TFV. TFV expands the schematic view over time. For example, your circuit might have a D flip-flop. In the schematic view, you would see one single flip-flop. In the temporal flow view, you would have a something like a snapshot of the instant right after each triggering clock edge. The flip-flop exists in every one of these snapshots, holding the simulated value at that specific time. Inputs of every snapshot may either come from the same snapshot, or can be fed by values of previous snapshots. So when the user sees an unexpected outcome within a snapshot, he/she can trace back either to an input of the circuit, or trace back in time, if that value was actually propagated from the past. And finally, when the user pinpoints the error cause from TFV, he/she can link to either the source code, the waveform or schematic view of that signal.Most of my work involves programming in C/C++, writing scripts in Python or Pearl, and since our tools is used for debugging hardware languages (Verilog, VHDL), so we would have to be familiar with them and would need to build small cases for testing purposes.