Naresh Narayanan Email & Phone Number

Redmond, Washington, Us

Redmond, Washington, Us

Design Verification lead for L2 cache in Microsoft custom CPU

Suwon-Si, Gyeonggi-Do, Kr

Load-Store unit verification for high performance custom mobile CPU.

San Diego, Ca, Us

Functional verification of high performance ARM v8.4 complaint L2 cache controller. Experience with constrained random verification environment using UVM methodology. Development of test plans, checkers, assertions and coverage to verify complex logic. Proficient in System Verilog, Perl, Verdi, Synopsys DVE.

San Diego, Ca, Us

Worked on verification of the CPU subsystem logic on multiple generations of Snapdragon mobile SoCs with focus on interrupt handling and distribution, power management and sequencing, debug trace and cross-triggers, clocks and resets. Verified the control logic that managed the clocks and power (Dynamic Clock and Voltage Scaling) of various CPU clusters in the industry's first ever 10nm server processor. Architected a constrained random UVM environment that found bugs which would have caused crashes on silicon. Supported post-silicon bring-up efforts leading to successful launch.

Santa Clara, California, Us

Development of functional testplans for new architectural features, holding testplan reviews with designers/architects, developing directed assembly language testcases at SoC level, analyzing functional coverage to fill verification holes, debugging critical failing testcases to root cause and analyzing the silicon impact.

Santa Clara, California, Us

Integration of major sub-IPs at SoC level, resolving cross-IP conflicts, branching & merging, triaging and debugging regression failures, integrating and validating bug fixes, optimization of sim performance, developing the testbench for new SoC models, maintenance of exercisers to support new design features and improving regression pass-rates to align with project goals.

Petersboro, Ut, Us

Worked with the perception team that does software design for the sensor framework (lasers, radars etc.) used in building autonomous vehicles. Performed software verification(C, C++) for ASI’s Obstacle Detection and Obstacle Avoidance (ODOA)/Perception products, integrating these products into the test vehicle and troubleshooting/debugging false failures

Chennai, Tamil Nadu, In

Worked on the engineering, research and development of ANUSAT, India's first university built micro-satellite funded by the Indian Space Research Organization (ISRO). Designed and tested a prototype of a magnetic torquer for the altitude control subsystem. Worked on implementing voltage control algorithms for the on-board power bus using micro-controllers.

Ms, Electrical Engineering

B.E, Electrical And Electronics Engineering