Naresh Narayanan Email and Phone Number
Naresh Narayanan work email
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Naresh Narayanan personal email
Design Verification Engineer with extensive experience working on state-of-the-art compute processors for mobile and server markets. Proven technical and leadership skills with a can-do attitude to work past barriers, collaborate across teams and delivery quality products that exceed customer expectations.Specialties: Strong understanding of CPU and memory sub-system architecture. Extensive background in System Verilog, C++, Perl, Python, UVM methodologies and verification infrastructure.
Microsoft
View- Website:
- microsoft.com
- Employees:
- 10
- Company phone:
- 0124 415 8000
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Principal EngineerMicrosoft Mar 2023 - PresentRedmond, Washington, Us
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Senior Design Verification EngineerMicrosoft Jan 2020 - Mar 2023Redmond, Washington, UsDesign Verification lead for L2 cache in Microsoft custom CPU
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Staff EngineerSamsung Sarc | Acl Aug 2018 - Dec 2019Suwon-Si, Gyeonggi-Do, KrLoad-Store unit verification for high performance custom mobile CPU. -
Staff EngineerQualcomm Nov 2017 - Aug 2018San Diego, Ca, UsFunctional verification of high performance ARM v8.4 complaint L2 cache controller. Experience with constrained random verification environment using UVM methodology. Development of test plans, checkers, assertions and coverage to verify complex logic. Proficient in System Verilog, Perl, Verdi, Synopsys DVE. -
Senior EngineerQualcomm Jan 2013 - Nov 2017San Diego, Ca, UsWorked on verification of the CPU subsystem logic on multiple generations of Snapdragon mobile SoCs with focus on interrupt handling and distribution, power management and sequencing, debug trace and cross-triggers, clocks and resets. Verified the control logic that managed the clocks and power (Dynamic Clock and Voltage Scaling) of various CPU clusters in the industry's first ever 10nm server processor. Architected a constrained random UVM environment that found bugs which would have caused crashes on silicon. Supported post-silicon bring-up efforts leading to successful launch.
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Senior Design EngineerAmd Jan 2012 - Jan 2013Santa Clara, California, UsDevelopment of functional testplans for new architectural features, holding testplan reviews with designers/architects, developing directed assembly language testcases at SoC level, analyzing functional coverage to fill verification holes, debugging critical failing testcases to root cause and analyzing the silicon impact. -
Design Engineer 2Amd Aug 2010 - Jan 2012Santa Clara, California, UsIntegration of major sub-IPs at SoC level, resolving cross-IP conflicts, branching & merging, triaging and debugging regression failures, integrating and validating bug fixes, optimization of sim performance, developing the testbench for new SoC models, maintenance of exercisers to support new design features and improving regression pass-rates to align with project goals.
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Intern Odoa/PerceptionAutonomous Solutions May 2008 - Aug 2008Petersboro, Ut, UsWorked with the perception team that does software design for the sensor framework (lasers, radars etc.) used in building autonomous vehicles. Performed software verification(C, C++) for ASI’s Obstacle Detection and Obstacle Avoidance (ODOA)/Perception products, integrating these products into the test vehicle and troubleshooting/debugging false failures -
Research AssistantAnna University Chennai May 2004 - Dec 2006Chennai, Tamil Nadu, InWorked on the engineering, research and development of ANUSAT, India's first university built micro-satellite funded by the Indian Space Research Organization (ISRO). Designed and tested a prototype of a magnetic torquer for the altitude control subsystem. Worked on implementing voltage control algorithms for the on-board power bus using micro-controllers.
Naresh Narayanan Education Details
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Texas A&M UniversityElectrical Engineering -
Anna University ChennaiElectrical And Electronics Engineering
Frequently Asked Questions about Naresh Narayanan
What company does Naresh Narayanan work for?
Naresh Narayanan works for Microsoft
What is Naresh Narayanan's role at the current company?
Naresh Narayanan's current role is Principal Engineer, Design Verification at Microsoft.
What is Naresh Narayanan's email address?
Naresh Narayanan's email address is na****@****oft.com
What schools did Naresh Narayanan attend?
Naresh Narayanan attended Texas A&m University, Anna University Chennai.
Who are Naresh Narayanan's colleagues?
Naresh Narayanan's colleagues are Vivi Lee, Hazem Taha, Nguyễn Ngọc Triệu, Glenda Dengah, Saurabh Bhatia, Bill W., Ishtiaq Dar.
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