Thanks for being on my profile.Myself:-From Kumbakonam (Tamilnadu) Done Bachelor's (ECE) & Master's on (VLSI DESIGN) under Anna University, after being trained for six months on Physical Design.Currently Exposure:-Working on 2NM node DDR 32xbit complex IP Taking care about PnR,PV,Timing closer.Previous Exposed:-Developing Generic Flow for 2nm,worked various Block and IP level for Different node'swhat I do:-All about Generic ways to solve the problem by directing the EDA Tool, To build the complex lower technology SOC Block/IPwhat I done:-worked on multiple lower nodes (5,4,3,2) understood the complex of each node and successfully completed 5+ Tape-out,work starts with synthesis, Floorplan, PnR, and well known about Timing and sign-off (PV,EMIR) & BUMP Planning complex RDL routes are know and gained knowledge and confidences.Skills:-EDA:-FC, ICC2 ,INNOVUS (common ui),CALIBER,SEAHACK,ICVLanguage:-TCL,linuxINTERST:-PnR, Timing closer, Placement.