Nasim Islam

Nasim Islam Email and Phone Number

Test Engineer Manager at ON Semiconductor
Nasim Islam's Location
Santa Clara, California, United States, United States
Nasim Islam's Contact Details

Nasim Islam personal email

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About Nasim Islam

Nasim Islam is a Test Engineer Manager at ON Semiconductor. Colleagues describe them as "Nasim worked with me the past four years while working for Onsemi. Nasim was an excellent leader supporting both New Product Development as well as Production Support for the Quantenna Business Unit (QCS) within onsemi. Nasim and his team were key contributors in the success of the QCS BU in which (at its peak) was generating +$240M in annual sales - considering Nasim's team consisted of 4 test engineers (himself included) this is an outstanding achievement. Nasim is a dedicated individual whom always prided himself, as well as his team, in completing their tasks efficiently while maximizing the test coverage to ensure outgoing Quality products." and "Nasim led and supported the QCS TE team while employed with On Semiconductor. Nasim executed his responsibilities very well within the QCS business in which he performed his functions exceptionally well. My direct involvement with him was related to his Test Engineering role. Within this role Nasim was an outstanding contributor in NPD ATE test-coverage, Yield improvement, and Test Capacity Improvements. Nasim's leadership and individual contributions was instrumental in the success of the Quantenna business and the eventual sale to ON Semiconductor. Nasim is a dedicated employee and demonstrates focus to his tasks and the health of the company and an outstanding asset."

Nasim Islam's Current Company Details

Test Engineer Manager at ON Semiconductor
Nasim Islam Work Experience Details
  • On Semiconductor
    Test Engineer Manager
    On Semiconductor Jun 2019 - Dec 2022
    Scottsdale, Arizona, Us
    As a manager of the test team: • engage various internal & external teams - ASIC, DFT, verification, system, SW, OSAT; for BGA/WLCSP devices. • Create test procedures, test-strategy from PRD, consult DFT team for better test-coverage • Predict test cost for marketing through parallelism, concurrency, throughput through ATE HW design optimization.Successfully developed test organization for a pre-IPO company, later became public • established industry standard Test & product organization • established TP environment configuration to stream-line test-program developmentOften led various cost-cutting projects with in-time delivery to help meet the financial numbers for the company.Generate schematic for optimized tester configuration for the project• lead external PCB vendors for ATE Final test and Wafer Sort Schematic & layout design• Signal integrity simulations (S11, S21, TDR, DDR/PCIe eye-diagram, PDN (Power Domain Network)) for Baseband & RF MIMO devices. Team up with Product management (PE) • for yield improvement with WAT data and with DOEs • support PEs with production/PVT activities, datalog generation, histogram chart to assess yield and process distribution analysis. Actively promote creation of modular test-scheme to my team members• for faster and efficient TP bring up by utilizing modules of other projects in common design-blocks across projects.Generate qual test program for reliability team and assist FA/reliability team with burnin HW debug for HTOL, ESD, & LU.Actively engage with Test Equipment Manufacturing Companies• to create synergy between business-unit future products and future test platforms – so that future product test requirements can be met by various test equipment manufacturing platforms as this is essential to meet technical challenges posed by future products, as well as to meet test-cost through throughput, parallelism & concurrency
  • Quantenna Communications
    Test Engineer Manager
    Quantenna Communications Aug 2017 - Jun 2019
    San Jose, California, Us
    Baseband & RF(WiFi) test engineerActed as a ATE Technical lead for complex SOCs with successful in-time completion of the project: * interfaces - DDR, PCie, SPI, I2C, SDIO, RGMII, UART* AFE - ADC/DAC (SLT on ATE)* RF transceivers 802.11(ac) - SLT on ATEActed as a ATE Technical lead for BB, MIMO 4x4, 8x8 devices with successful in-time completion of the project.
  • Quantenna Communications
    Senior Test Development Engineer (Mts)
    Quantenna Communications Oct 2014 - Jul 2017
    San Jose, California, Us
  • Siliconimage
    Senior Test Engineer
    Siliconimage Aug 2005 - Oct 2014
    * Test Engineering Responsibilities• Currently working with BB & RF group for test coverage, DIB design guidelines, test methodology for 60GHz RF and Base Band MCM Products• Worked on the test coverage and test strategies with design team for Bridge product – SATA I & II to PCI-e, storage processor, HDMI port-processor• Generated cost structure for the production test cost• Implemented experiments with designers to bring up new products into market• Generate and implement test program for new products and interact with overseas production site for mass production of new devices• Generate characterization test program and collect characterization data - AC & DC perimeters - across the corners for new devices• Proficient in shell scripts to bring about efficiencies to manipulate characterization data to assess yield for new device• Guide load vendors for design, and debug high speed load board* Assembly & QA* New Product Characterization / Validation* Debug Analysis
  • Integrated Device Technology Inc.
    Test Engineer
    Integrated Device Technology Inc. Aug 2000 - Aug 2005
    San Jose, Ca, Us
    • Generate Test Plan for CISCO 18M Internet protocol co-processor, IDT IP-coprocessor • Silicon debug and characterization• Establish manufacturing guard-band and perform tester to bench correlation• Work with design engineer to develop Design-For-Test patterns to integrate functional capability of testing in silicon• Implemented experiments with designers to bring up new products into market• Performed competitor analysis of comparable devices as part of Marketing feasibility studies.

Nasim Islam Skills

Testing

Nasim Islam Education Details

  • California State University, Northridge
    California State University, Northridge
    Ee

Frequently Asked Questions about Nasim Islam

What is Nasim Islam's role at the current company?

Nasim Islam's current role is Test Engineer Manager at ON Semiconductor.

What is Nasim Islam's email address?

Nasim Islam's email address is na****@****est.com

What is Nasim Islam's direct phone number?

Nasim Islam's direct phone number is +166920*****

What schools did Nasim Islam attend?

Nasim Islam attended California State University, Northridge.

What skills is Nasim Islam known for?

Nasim Islam has skills like Testing.

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