BIOS Design and Firmware Development, Xeon Intel Architectures, Embedded Linux & ARM, BMC, PCIe, PIC microcontrollers.

• Rapidly inspected, understood, and supported highly complex SystemVerilog modules.• Maintained and enhanced modules for DOCSIS chipset including packet resequencing, DDR management and buffering, complex filtering mechanisms, and quality-of-service routing.• Analyzed both UVM and non-UVM verification environments and suggested improvements for higher efficiencies, increased coverage, and improved model-to-RTL consistency.• Debugged a catalog of bug reports and implemented fixes for edge-case scenarios found in regression testing.

Design• Managed top-level FPGA documentation, change management, timing closure, and full release cycle for multiple large-scale FPGAs simultaneously (Xilinx Virtex-6, Virtex-7).• Implemented various high performance designs including 10G Ethernet MAC, 10G DOCSIS Decoder, various dataplane schedulers, gearboxes, QoS modules, and debug interfaces.• Designed multiple SERDES interfaces including 10G XAUI with configurable line rates and 12.5G FPGA-to-ASIC backplane interface.• Solved multi-die challenges presented by largest Xilinx parts (Virtex-7 2000T and 1140T) including floorplanning, advanced Vivado features, synthesis directives, strategic pipelining, and device specific coding strategies.• Supported embedded processor designs including embedded software design and custom driver development. Wrote C algorithms and documentation for controlling various peripherals over I2C, S2W, MDIO, and custom protocols (clock generators, SFP/SFP+ management, 10G PHYs, crosspoint switches, flash memory, CPU error detection).Support• Wrote scripts for automated lab testing, version control enhancements, and log file analysis (Bash, perl, makefile, tcl).• Maintained FPGA backend toolsets in a Linux environment, including VCS simulation, Synplify Pro, ISE/Vivado, and version control systems.• Designed, implemented, and maintained a complete cable modem testbed to support local and remote system level testing (traffic generators, CMTS, RF network, cable modems, power cyclers, terminal servers).

• Secret clearance as a civilian engineer.