Nathan Muller Email & Phone Number

Boise, Idaho, United States

I design physical layout for DRAM memory IC circuits. My experience in a range of industry standard EDA tools and associated programming/scripting languages is applied to advanced designs.

Pocatello, Idaho, United States

I specialize in the entire integrated circuit (IC) physical design process, spanning from RTL (Register Transfer Level) to GDSII (Graphic Data System II) for both individual blocks and top-level digital and mixed-signal devices. My expertise includes floorplanning, power grid analysis, place and route, clock tree synthesis, timing closure, GDSII stream-out, and physical verification (DRC, LVS, Antenna, ERC, DFM) to ensure accurate delivery for reticle data preparation.

Pocatello, Idaho, United States

I work with experienced engineers to learn and understand the tools and concepts of digital layout design and implementation within the semiconductor manufacturing industry.

Rexburg, Idaho, United States

Oversaw lab efforts for 30 electric circuit analysis students and provided grading and feedback on submitted lab reports.

Rexburg, Idaho, United States