Integrate different RTL/Verification IP's to form top level Soc environment. Involving C++, SystemVerilog OVM modules which including scoreboard, monitor, functional coverage, infra-structure and random generation.

* Digital lead in WiFi handset control w/ embedded DSP core. Specified peripherals, analyzed AHB bus performance, standardized RTL implementation and block/chip level test architecture, wrote the timing constraint scripts, oversaw synthesis, timing closure, and functional verification. Lab debug with FPGA board. Wrote Verilog RTL for: External memory controller, DMA control block embedded in AHB, SPI (serial peripheral interface) and parallel bus interface, UART, AHB Arbiter, Host Command Interface, Interrupt controller, and AHB compliant peripherals.* Digital Lead in PWM codec connecting DSP core to DAA. * Verification Architect. Developed mixed-signal test bench for chip/block with BFM’s. Has signal generator and signal analyzer BFM’s w/ FFT/IFFT. Integrated with Matlab models for analog circuits. Wrote BFM’s: FIR filters, delta-sigma converter for ADC/DAC; PCM/GCI, parallel, command bus, AHB master, slave, monitor BFM. BFM’s allow randomization and functional coverage by Specman e or SystemVerilog.

* Developed in-house standard cell characterization tool and generated library files.* CAD tools support (Verplex, Design Compiler, PrimeTime, TimeMill, PowerMill, Arcadia, LVS, DRC), maintained and update process technology files. Developed script (csh/perl/dc/ skill) or C for nelisting design and design automation.* IP integration of South Bridge. Modified IP (PCI, RAM interface), synthesis, timing closure, test bench integration, logic simulation, and test plan closure.

* X86 Assembly code development for verification of new X86 processor.

* Specified OnNow support on a 100 BaseT Ethernet control chip (PCI interface), joined the spec committee, RTL design w/ VHDL synthesized, verified w/ simulation.* Process shrink of a 10 BaseT Ethernet chip (ISA w/ PnP). RTL design, verification, circuit design a 4K SRAM, I/O pads, timing, layout supervision, test generation, and silicon debug.