• Supported Tier1/Tier2 Semiconductor companies.• Visited MediaTek Singapore for training and testchip kickoff in 2019.• PI signoff for advanced tech node design. Worked very closely with Co-designer , memory designer, Power pattern and APR team.• Provided 3 months onsite support at MediaTek Taiwan during 2017.• Account Management, Proliferation and pre-sales.•Product Support and Customer Training•Next Generation Product Engineering

• Supported Tier1/Tier2/Tier3 Semiconductor companies.• Provide full time support to multiple semiconductors companies in PI drop analysis for SoC as well as Custom Design.•Provided 1 month onsite support at MediaTek Taiwan in 2015.•Provided 3 months onsite support and eval activities at MediaTek Taiwan in 2016.• Complete ownership of Apache TechFile delivery for 14nm,22nm,28nm,40LP,55nm,65nm,130nm and 180nm for GlobalFoundary.• Clock tree Correlation-RH vs Spice • 14nm/22FDSOI RedHawk reference flow development for GF. Validated EM rules and resistance calculation.

• Worked on re-spin of 28nm SOC-Gate level ECO,Signal EM for IP's and SOC,Physical Verification activities.• Worked on Static/Dynamic and Power EM analysis of 28nm SOC.• Proficient in closing DRC/LVS/DFM/ERC/Chip finishing activities on subchips. Hard IP's and complex SOC's.• Involved in next generation flow development and driving methodologies for Physical Design.• Mentoring junior engineers.

• IR optimization of Wire-Bond design:Enabled Core + Jumper bonding to meet higher performance on Cortex A8 ARM Core. Achieved IR drop reduction upto 45% on Static and 30% Dynamic with Package Parasitics after various iterations. Analysed and identified bottle necks(ARC Closure, Pkg DRC and Substrate routing) to achieve closer to GHz on Cortex A8 ARM core with higher OPP’s with the Core + Jumper bonding.• Cortex A9 ARM hardening activity:Floorplanning and Optimization of Power Routing of MSMV design to improve run time/performance.Power Estimation, Power grid Analysis, Grid robustness,Resistance and EMIR Closure (Statics and Dynamic) along with top level feedback.CPF creation/validation for MSMV design.Routing optimization iterations. Expertise in Signoff checks closure-Physical Verification,ETS-Noise,Antenna,ESD,ERC,CLP and DFM .• Mentoring junior engineers• Gate level ECO Implementation and Timing closure/Chip finishing activities of subchips• PD training (Netlist to GDSII) for a team of 6 members.

• HDL-Verilog,System Verilog,VHDL.• Protocols:AMBA,SPI,Ethernet,I2C,Ethernet MAC.• Code coverage analysis for IP's.• Testchips - 130nm,45nm,40nm and 28nm.• Die size Estimation and IO Ring Creation (Unique Dual IO Ring for a wirebond design and complex IO Ring) for various Test Chips at 130nm,45nm,40nm and 28nm.• FloorPlanning,Power Routing,PnR and Gate level ECO implementation full chip designs.• Physical Verification and Reliability checks -Subchips/Fullchip.

Worked as RA in IIsc