Rtl Design Engineer 1
CurrentSoC: ARM Voyager R1 - Annotation to RTL based on clock, reset information from specification.- CDC, RDC Constraints generation for the RTL.- Scripting to run CDC/RDC for the RTL. - Analysing the reports and fixing violations.Tessolve Centre of excellence:- UART IP development: RTL design in verilog and MAS development. - Generic FIFO design for IP's: RTL.