Naveenkumar Mohan Email & Phone Number

Chennai

SoC : ARM Voyager R1 - Annotation to RTL based on clock, reset information from specification.- CDC, RDC Constraints generation for the RTL.- Scripting to run CDC/RDC for the RTL. - Analysing the reports and fixing violations.Tessolve Centre of excellence :- UART IP development : RTL design in verilog and MAS development. - Generic FIFO design for IP's : RTL design in verilog and MAS development . Lint check. - JTAG IP : IP development based on IEEE 1149.1, worked on MAS document and RTL development for its Sub-modules.

Electronic City, Bangalore

Master Of Science - Ms, Electrical And Electronics Engineering, Merit

Areas of study include Advanced 5G wireless communication, MIMO systems, URLLC with massive MIMO connectivity, VHDL design with spartan 6.

B.Tech, Electrical, Electronics And Communications Engineering, First Class

Areas of study include Digital communications, Circuit theory, Antennas and propagation, Wave guides, Wireless communication, Signal.