Teaching assistant for three courses i.e., Digital Logic Design, Digital Communication and Digital Signal Processing under the guidance of Dr. Tom Derryberry. Assisting students in the coursework and working along with the Grader.

Served as a student assistant for multiple courses, i.e., Signal and Systems, System Modeling and Simulation and Control Systems Design under the guidance of Dr., Tom Derryberry, Professor Yusheng Wei and Dr., Guturu Parthasarathy, my role involved making substantial contributions to students' academic achievements.

Tenorsys works with Degirum's Sandiego-based chip design team, which develops AI inference chips. Tenorsys verifies Degirum’s SOC, demonstrating a commitment to Emerging Technology. Developed a comprehensive test plan and C test cases to verify the functionality of SoC-level I/O blocks, including UART, QSPI, I2C, and GPIO. Verified interrupts using ISR routines and debugged connectivity issues within wrappers and verification environments. Implemented sequences and tests using JTAG VIP in UVM, performing memory and register write/read operations. Verified clock generation and PLL functionality across various configurations, emphasizing the importance of Timing in design verification. Executed MBIST operations on SoC memories, configuring registers, injecting errors at memory corners, and analyzing repair rejections to ensure Correctional action.

Understood PCIe specifications and designed a UVM-based verification environment for the Data Link Layer module at the IP level, developing comprehensive test cases to cover all functional features and debugging issues throughout the verification process. Verified a 16x16 router using SystemVerilog and UVM, ensuring reliable performance and functionality. Successfully designed and verified a 16x128 DRAM module, showcasing strong attention to detail and verification expertise. Created a digital alarm clock using Verilog, achieving accurate and successful output verification.