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Tech lead for the SHAKTI Microprocessor Programme at RISE LAB

My thesis has explored various domains of approximate computing.In this thesis I explore 3 major design paradigms and methodologies which leverage approximate nature of applications and provide alternative power and/or energy efficient hardware solutions. The first proposed work deals in the domain of approximate computing and proposes an application independent automated flow that converts a given design into an approximate version using novel voltage scaling or power gating techniques. The proposed model also encompasses automated techniques to identify gate level logic which can be leveraged for approximations. Post identification, the model utilizes a series of physical optimization techniques to lead to a tunable circuitcapable of operating in both accurate and approximate modes based on environmentand user constraints. The second work in this thesis deals with using Stochastic Circuits as fault checkers for approximate applications. The key benefit of stochastic checkers is the intrinsic compactness offered which leads to upto 30% area and upto 21% power reductions for various benchmark circuits. The work also proposes a set of optimizations to deal with limitations of the stochastic checkers such as - fault coverage, falsepositives and high latency.The final work focuses on adopting nano-oscillators for performing digital computations for certain approximate applications. The proposed architecture is generic in nature and executes a set of instructions which have been commonly found to be dominant kernels in major approximate applications. The framework has been demonstrated for Vector Quantization in the speech recognition domain and has notedly shown drastic improvements in power with negligible reduction in output quality.

Currently working on the design and development of various class of processors supporting the RISC-V ISA by Berkeley. More info can be found at : https://bitbucket.org/casl/shakti.Worked on the development of a full-fledge indigenous 32-bit RISC Processor using BLUESPEC. The ISA has 150+ instructions. Contributed to the design of the complete MMU design, supporting multiple page sizes, 3 level page table walk, pre-cache buffer etc. as well the core itself. Also developed a full 32bit micro controller for a secure SoC.

During my internship at Texas Instruments Bangalore, I had worked primarily in my research area - Stochastic/Approximate computing. In the 6 months of internship I was able publish 2 papers, communicate a third paper and also publish a patent.

BLUESPEC verification of a multi-million gate design : BLUESPEC is a High-level Synthesis Language. The design consisted of 4 CPLDs completely designed in BLUESPEC and formally verified with the Verilog counterpart of the same design through Formal-Pro.

Development of a VHDL test-bench for one of the BARC's safety critical systems.The code was synthesized on ACTEL's FPGA and real-time simulations were carried out.