Junior Research Fellow
Current• RTL Design and implementation of a high resolution Sinusoidal Synthesizer using AMD Vivado on Artix-7• RTL implementation of SPI protocol to communicate to external components• Hands-on training sessions on IP packaging, Block Design approach, HDL Wrapper generation and Vitis Flow for embedded design• Acquired knowledge in PYNQ python productivity, STA, CDC, Debug Techniques, and HLS