Build from scratch the Verification Environment for a new Power Management IC (Makalu)- Development of multiple module level Verification environments (FSM, Safety management controller, )- Development of TopLevel infrastructure- Integration of modules Verif envs into top level- Integration of different analog/behavior models in TB- Prepared PVS (Product verification specification) and PVR (product verification reports) for the chip requirements/ Hold presentations supporting the team with building it aligned in the whole project- Planned the activities for the tasks , assignaments, estimations, Jira, Jama updates.

Functional block level Verification for a complex PMIC DCDC (dig+ana)- Development of the ENV from scratch uVM based- mixed signalLeading activity on module level Verification for 2 other modulesInvolved in TopLevel Verification and integration.Reviewer of VEs workHelp to ramp-up new employees

Functional block/Top level Verification of DWC_DDR_UMCTL5 (DDR5/4 Controller (DDRCTL) combined with a DWC DDR PHY is a complete memory interface solution for DDR memory subsystems) • SV-uVM Verification Development : tests, checking mechanisms, drivers, monitors, scoreboards, coding/collecting/analyzing FCOVe, adding assertions • Customization of CTRL for new features for different Customers (most of them for Automotive). • Support the team with implementation guidance. • Added ISR support for different interrupt sources. • Hosted regressions and coverage meetings, provided functional coverage analysis and assigned tasks to appropriate engineer. • Reviewer for code-collaborator reviews in my area of expertise. • Updated scripts • Updated documents (Databook, UserGuide)

Functional block/Top level Verification for DWC_ddr_umctl2 (DesignWare Cores Enhanced Universal DDR Memory Controller) • uMCTL2 verification tasks (adding tests, checking mechanisms, updating drivers, monitors, scoreboards, coding/collecting coverage, adding assertions, minor RTL changes required). • Automotive features : parity, ecc – UVM environments • uMCTL2 scripts uptates. • uMCTL2 documents updates (Databook, UserGuide)

Senior Verification EngineerTeam LeadMember of Technical Staff/People management

Functional block level Verification for MSP432 eCPU - LDU (Local Debug Unit)- Perform block-level metric-driven verification using Specman e language and eRM methodologyFunctional block level Verification for MSP432 eCPU - GDU (Global Debug Unit)- Perform block-level metric-driven verification using Specman e language and eRM methodology

Subsystem level Verification for OMAP 5 - PUSS (PCI USB SubSystem)Top level verification for PCIeMAC part from PUSS, SystemVerilogAdding tests and checking mechanism for PCIe, SystemVerilog

Functional module level Verification for DAFE (Digital Audio FrontEnd) - uVM based

Functional Block Level Verification for CC2505 (Developed from scratch complete uVC’s)Functional Block Level Verification for CC1120 (Developed from scratch complete uVC’s)Top Level Verification for CC1120 and CC1200 (Writing tests, adding checking mechanisms, collecting and analyzing coverage, uVM based.)

Verification IP’s development for multiple interface (developed the Verification Strategy, Coverage Plans and Test Plans)