Fpga Engineer Ii
Current- Developed FPGA-based DDR SDRAM diagnostic tools using VHDL, and guided corresponding Python design, resulting in valuable recovery of malfunctioning network product inventory- Led implementation of PON, I2C, and SFP FPGAs in a 1G/10G combo-PON product- Drove effort to convert legacy FPGA project RTL and their corresponding TCL, Python, and C shell scripts to Git- Maintained and developed features for on-product Python scripts to assist in FPGA field debugging- Diagnosed product failures from FPGA field logs and debugging live customer systems- Mentored four undergraduate interns/co-ops in RTL design and FPGA workflows