Senior Analog Design Engineer
Current- Proficient in designing high-speed DDR IO interfaces and low-power interfaces across various technologies including 4nm,7nm, 12nm, 22nm, 28nm, 40nm, 55nm, and 65nm. Expertise includes transmitter, receiver, calibration, amplifier, level shifter, biasing current source, voltage reference, PLL, Delay Line and ESD.- Proficient in SI/PI simulation using IO.