PhD research work with Professor Elyse Rosenbaum:- Developed IEC61000-4-2 system-level testing setup and techniques for real-time measurements of ESD stresses within a system.- Worked to utilize and improve SEED methodology for ESD protection design.- Designed devices and circuits for a test-chip to be used to discover causes of soft-failures during and after an IEC61000-4-2 stress. - Investigated soft/hard-failures within a functioning system containing sensitive logic, memory elements, and high-speed interfaces.- Designed novel on-chip supply voltage measurement techniques to determine max under-voltage and over-voltage for 3.3 V IO domains and 1.2 V core domains during electrostatic dishcarge (ESD) events.- Developed soft-failure monitors based upon sequential logic elements to study correlation of soft-failures to supply-voltage fluctuations that occur during system-level ESD events.MS research work with Professor Elyse Rosenbaum:- Designed wafer-level ESD-event emulator to deliver a high-current pulse with variable pulse-width and fall-time to study the turn-off effects of ESD protection devices, especially those with snap-back, and to accurately measure the holding-voltage and current.- Modeled the above emulator to fully understand the charge movement and to allow accurate devices simulations over the ESD time-scale.- Designed and simulated circuit layout for 3D-IC ESD characterization.

Developed a novel 25 Ω charge-device model (CDM) testing method to reduce discharge-waveform variability when testing advanced technologies at low CDM levels.Analyzed system-level electrostatic discharge waveforms to determine the stress current seen by the device under test.

Collected data regarding the response of devices from various technology nodes to stress from electrostatic discharge to ascertain how certain characteristics scale with the the technology nodes.

Made further advancement to the design of automated electrostatic discharge emulation systems.

Designed and constructed an automated human-body model/transmission-line pulse (HBM/TLP) electrostatic discharge emulator to be used for IC failure reasearch. Worked with production wafers for electromigration qualification and ESD failure analysis with very-fast TLP (VF-TLP). Automated a wafer-level charged-device model (CDM) emulation system.

Designed computer user interfaces for use in defense equipment. Detected and corrected a software bug within a vehicle control unit that prevented proper update of vehicle control software.

Carried out the complete design of factory automation machinery from planning and CAD to hardware installation and troubleshooting and ultimately to the programming of PLCs to control the machinery.Worked with a team to retrofit old machinery with new control systems to speedily return to system to production.Routinely updated control systems for various fabrication systems ranging from automated defect detection using computer vision to foundry controls for injection molded aluminum parts to correct for errors that arose during manufacturing.