Created and executed test plan for newly architected distributed self-test control unit (STCU) on a 12-core functional safety NPI SoCDeveloped a new VIP for STCU with SV checkers, C stim, & UVM sequences for reusability and to support the IP’s new architectureEnabled legacy scripts in a new UVM SoC testbench environment to instantiate clock and reset checkers for STCUCommunicated frequently with design, DFT, and architects to discuss defects and to solidify STCU specifications at the SoC levelDebugged issues in RTL related to functional isolation/safe stating, resets/reset domains and clock gatingEnhanced and maintained existing CI flow, used by DFT and DV teams (consisting of 40 people), using Jenkins/VManager/Perl/ShellWrote new and enhanced existing scripts for an SoC verification regression flow, using VManager and Python/Perl/Shell scriptsImplemented python scripts to automate toggle coverage exclusion, clean up testbench files, and vplan/test argument generation

Teaching Assistant for Digital Systems Design using Verilog

Developed shell scripts to automate population of the TB environment and to run sanity checksDebugged compile errors in testcases in the verification environment using logfilesCollaborated with test engineering team about user interface of script to improve script