Responsibilities entail design, layout, BOM optimization, converting feature set requirements into schematic involving digital and analog circuit design, schematic capture, component selection and perform relevant and necessary simulation for critical signals and power rails. Early involvement on package quadranting, breakout/ballmap design with drive critical floor-planning decision thru feasibility study placement/reusability percentage to achieve cost competitive advantage. Co-work with multiple teams such as the platform architect, Signal Integrity, mechanical, thermal, package design, DFT and DFM. Review & define PCB layer structure through PCB technology study and discussion with PCB maker to meet targeted impedance. Design Interposer to support “early reference board” to evaluation before received actual silicon Responsible as final gate to oversee design/layout review, Tape-out Gerber with go-thru necessary checklist and ensure design meeting development concept requirement.

• Speed-up overall design cycle by implement process improvement.• Established ECAD tools with significate cost reduction.• Setup ECAD tools, such as customize function key & create automation script.• Created basic script/skill for OrCAD.• Created and maintained libraries for PCB design and schematic entry• Defined PCB layer structure through PCB technology study and discussion with PCB maker.• Explored project requirement and evaluated various kind of ECAD software evaluation, which improved process cycles.• Supported the development of the PCB from conceptualization, verification &qualification to post productions.• Designed from schematic to layout through internal design review (DFM) with respective functional teams and vendors (EQ)• Experience on Capture CIS, Cadence OrCAD PCB, AutoCAD, Altium (beginner), view mate Pro and Knowledge on Cadence Skill code.• Participated in Cadence OrCAD PCB Designer Training on 20Feb2017

• Participated in PCB technology study such as define PCB layer stack-up, HDI via technology, design guideline, Board area estimation/panelization, routing topology, rules constrains as well as signal integrity simulation to determine the best performance and most cost effective approach for platform designs.• Design schematic tool route/replace component/ replace connector in schematic• Experienced in designing a wide range of high complexity multi-layer HDI boards and Flexible PC• Ability to route controller and RF base on RF/Controller Engineer excel/constraint.• Involved design from schematic to layout through internal design review with respective functional teams and vendor • Involved in support the development of the PCB form conceptualization, verification and qualification to post productions.• Participated in negotiation PCB fabrication process lead time, cost and schedules delivery.• Experienced in using CAD for almost 7 year.• Experienced on Cadence allegro design entry HDL, and constraint manager.• Experienced with Agile. (For Design achieve, PCB qualification process, print acceptance and etc)• Ability to create basic script/skill for Cadence Allegro.• Problematic PCB solving and form guidelines base on lesson learn• Problem-solving on FLEX/PCB issues. • Trained and coached new hire/ junior PCB • Presented PCB related technical Paper in Motorola Solutions Tech-expo.• Presented Lean ideals to enhance efficiency on layout cycle time. • Obtained IPC Certified Interconnect Designer (CID) on 11 April 2014.

• Managed the component library group• Created schematic symbol• Created component footprints. • Checked existing footprints for accuracy. (Checklist) • Designed schematic• Placement and Routing PCB• Knowledge of PCB CAD software. (CR5000; UNIX and window base)• Knowledge of PCB CAM Viewer GCCAM.• Document of DFMEA, PCB checklist and Footprint checklist.• Ability work independently or in group.