Most recently I have been doing mostly pre-silicon verification utilizing UVM for blocks inside of Microsoft custom silicon projects including XBox, Hololens, and custom server silicon. This includes initial architecture review to help drive design decisions to improve design robustness and ease of verification. I have owned and driven numerous UVM testbenches from concept to completion including verification test plan development, test bench implementation, and coverage closure. I have the flexibility to work and assist on multiple projects concurrently and have been able to quickly ramp up on new projects, assess the existing issues where necessary in order to create & implement a solution to the problem.In addition, I have also worked on both unit and chip level verification of custom silicon utilizing a Microsoft developed C/C++ chip level verification environment which is used for pre-silicon chip simulation/emulation as well as post-silicon validation efforts.I have experience in digital functional hardware verification of server storage & IO adapter ASICs & SoCs for IBM's Server Technology Group (STG). I have experience developing a verification environment for a MESA cycle based simulator, writing the verification environment code as well as enhancing and modifying pre and post processors (PERL) for the unit simulation with consideration for full chip simulation. This environment is IBM's proprietary Fusion Reuse Methodology (FRM) which is very similar to Cadence's OVM/UVM in that it has monitors, drivers/transactors, and checkers. In addition to coding the environment, I have experience in writing directed & constrained random tests to verify the logic based upon a verification plan derived from the product specifications & user's guide.Specialties: I have experience in working with a C/C++ based chip level verification environment designed internally at Microsoft. In addition to this chip level verification, I have worked with UVM to do unit/block level verification. I have experience in developing and maintaining a MESA based environment that integrates drivers/transactors, monitors, & checkers. The environment uses a cycle based simulator to test out functionality of RTL logic using IBM's proprietary Fusion Reuse Methodology (C/C++ based & has PERL pre/post processors), which is similar to Cadence's OVM/UVM.