Pmo
Current
Sep 2013 - Present
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Nicolas Verkinderen Email & Phone Number
PMO at SWING-WS
at
Swing-WS
LinkedIn matched
✓ Verified August 2026
3 data sources
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Current company
Role
PMO at SWING-WS
Location
Greater Nice Metropolitan Area, France
Company size
Who is Nicolas Verkinderen? Overview
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Nicolas Verkinderen is listed as PMO at SWING-WS at Swing-WS, a with 20 employees, based in Greater Nice Metropolitan Area, France. AeroLeads shows a matched LinkedIn profile for Nicolas Verkinderen.
Nicolas Verkinderen previously worked as PMO at Swing-Ws and MGTS, STA principal engineer, special projects manager, SoC and methodology expert at Texas Instruments France. Nicolas Verkinderen studied at Certifications.
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Swing-WS
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Profile bio
About Nicolas Verkinderen
Nicolas Verkinderen is a PMO at SWING-WS at Swing-WS. He possess expertise in asic, soc, static timing analysis, integrated circuit design, ic and 15 more skills. Colleagues describe him as "I hired Nicolas in 2003 and have been his supervisor since then. Nicolas has developed an outstanding and unique expertise in STA and timing of complex SOCs for which he is recognized and well respected in TI and in our industry. In addition of his technical expertise, Nicolas has shown remarkable abilities to drive people and projects. He is very talented, autonomous, well organized, result oriented and a hands-on achiever. He is always pushing innovation, going the extra mile when… Show more" and "He led to define key STA requirements and also executed high acculate STA tasks which was positively ettected to my DFT task in our project."
Listed skills include Asic, Soc, Static Timing Analysis, Integrated Circuit Design, and 16 others.
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6 roles
Nicolas Verkinderen work experience
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Mgts, Sta Principal Engineer, Special Projects Manager, Soc And Methodology Expert
28nm hold measurement testchip- project management and 12-engineer virtual team manager- Concept definition, designed the hard-macro; full-flow with RC/EDI/ETSCompany-wide Cadence transition- Technical manager of the transition from Synopsys to Cadence for timing tools. - Settled a cooperative environment between Cadence and TI- Implemented readiness strategy & coordinated the TI teams activity- Drove major innovations (ETS-ECO, AOCV, user-ability, …)Company-wide best-practice sharing and alignment- The alignment allowed all design teams to benefits from the best available practices, increased the overall efficiency and enabled IP sharing across BUs. - 20-expert virtual team manager- Design In eXcelence STA-Margin milestone checklist owner- Implemented clocking, timing budgeting & STA constraints design guidelines- Drove the creation of the automated STA flow- Supporting STA teams in France, USA, India, Israel and JapanNice STA group- Recruited and managed a group of 15 engineers - Multi-site organization, project planning, task/execution tracking- Trained team members to become STA experts & team leadersSilicon projects- Markets: wireless mobile, multi-media & tablets- Technical roles: STA lead, PrimeTime & STA trainer, implement STA & timings closure strategies, platform architecture evolution (clocks, IP-reuse, DFT & power mgt, asynchronous-bridges, chip-interfaces)- Projects: OMAP2/3/4/5/6 platforms, OMAP2420, OMAP2430C, N3G2, ECosto, Wrigley3G, Attila, OMAP4430, OMAP5430, OMAP6430. IPs: ARM A9/15, GFX, interconnects.- Technologies: 90/65/45nm & 28nm- Technical specificities: >10M instances, hierarchical SoC, 200MHz/1GHz, >250 clocksInnovation and methodology for the future- Investigated SSTA, pulse latches, 3D-SoC partitioning & context aware STA.Conferences- Presenter, chair, committee and/or organizer at international (SNUG, VARI, CDNLive) and internal conferences; SNUG2009 best paper
Jul 2003 - Aug 2013
Asic Designer; Digital Team Leader
Designed a very low power mixed-signal ASIC (0.35µ HighVoltage process). This single chip solution is driving mobile phones color active-matrix Liquid Cristal Display.Managed and trained a team of 6 digital engineersOrganized the digital activities (tasks splitting, resources, schedule, tracking), cooperation with the analog teamFeasibility study, chip floorplanning, new digital architecture definition, specificationsRTL design, verification, synthesis, place & route, STA, silicon wake-up.Deployed digital design practices and ensured high quality execution
Jul 2002 - Jul 2003
Sr Engineer; Asic Technical Expert
I started as Static Timing Analysis (STA) engineer on a key project and became quickly one of the few STA experts at Ericsson, supporting projects company-wide. I extended my expertise to the rest of the design flow.Technical roles: STA, timing closure, place and route, synthesis, RTL redesign for quality and design. Offsite STA support & teacher and ASIC technical expert support. ASIC vendor/foundry technical interface.Technologies: IBM/LSI/Philips 180/130/110nm & FPGATechnical specificities: 12 silicon projects/chips, up to 3.2M row logic gates, 5.6Mbit of on chip memory, 270MHz, multi-clock My roles in the projects evolved quickly to technical leader positions, I also had the chance to setup and managed the EADP international and multi-team project.I learnt a lot from the 12 silicon projects I worked on in Sweden, Norway, Germany and Italy: management styles & techniques, inter-cultural conflicts, multi-site technical organization.Roles: ASIC leader, project manager, Request For Quotation, pricing and IP reuse contract negotiations
Aug 1999 - Jul 2002
Trainee
Digital ASIC designer in the Microelectronics section of the Control, Data and Power division (Noordwijk - The Netherlands)Worked on the next generation ESA ground-spacecraft communication component.Designed, in VHDL, the telecommand decoder core and created self-checking test benches for the decoder.
Jan 1999 - Jun 1999
Trainee
Digital ASIC designer in the Digital Media Broadcasting (DMB) department (Caen - France)Worked on an MPEG2 decoding component for digital TV. Designed a spy-bus (snoopy-bus) in VHDL which allowed study and evaluation of the component.
May 1998 - Aug 1998
2 education records
Nicolas Verkinderen education
Education record
Certifications
Engineer, Electronics
FAQ
Frequently asked questions about Nicolas Verkinderen
Quick answers generated from the profile data available on this page.
What company does Nicolas Verkinderen work for?
Nicolas Verkinderen works for Swing-WS.
What is Nicolas Verkinderen's role at Swing-WS?
Nicolas Verkinderen is listed as PMO at SWING-WS at Swing-WS.
Where is Nicolas Verkinderen based?
Nicolas Verkinderen is based in Greater Nice Metropolitan Area, France while working with Swing-WS.
What companies has Nicolas Verkinderen worked for?
Nicolas Verkinderen has worked for Swing-Ws, Texas Instruments France, Philips Semiconductors Gmbh, Ericsson Utvecklings Ab, and European Space Agency.
How can I contact Nicolas Verkinderen?
You can use AeroLeads to view verified contact signals for Nicolas Verkinderen at Swing-WS, including work email, phone, and LinkedIn data when available.
What schools did Nicolas Verkinderen attend?
Nicolas Verkinderen studied at Certifications.
What skills is Nicolas Verkinderen known for?
Nicolas Verkinderen is listed with skills including Asic, Soc, Static Timing Analysis, Integrated Circuit Design, Ic, Rtl Design, Semiconductors, and Eda.
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