28nm hold measurement testchip- project management and 12-engineer virtual team manager- Concept definition, designed the hard-macro; full-flow with RC/EDI/ETSCompany-wide Cadence transition- Technical manager of the transition from Synopsys to Cadence for timing tools. - Settled a cooperative environment between Cadence and TI- Implemented readiness strategy & coordinated the TI teams activity- Drove major innovations (ETS-ECO, AOCV, user-ability, …)Company-wide best-practice sharing and alignment- The alignment allowed all design teams to benefits from the best available practices, increased the overall efficiency and enabled IP sharing across BUs. - 20-expert virtual team manager- Design In eXcelence STA-Margin milestone checklist owner- Implemented clocking, timing budgeting & STA constraints design guidelines- Drove the creation of the automated STA flow- Supporting STA teams in France, USA, India, Israel and JapanNice STA group- Recruited and managed a group of 15 engineers - Multi-site organization, project planning, task/execution tracking- Trained team members to become STA experts & team leadersSilicon projects- Markets: wireless mobile, multi-media & tablets- Technical roles: STA lead, PrimeTime & STA trainer, implement STA & timings closure strategies, platform architecture evolution (clocks, IP-reuse, DFT & power mgt, asynchronous-bridges, chip-interfaces)- Projects: OMAP2/3/4/5/6 platforms, OMAP2420, OMAP2430C, N3G2, ECosto, Wrigley3G, Attila, OMAP4430, OMAP5430, OMAP6430. IPs: ARM A9/15, GFX, interconnects.- Technologies: 90/65/45nm & 28nm- Technical specificities: >10M instances, hierarchical SoC, 200MHz/1GHz, >250 clocksInnovation and methodology for the future- Investigated SSTA, pulse latches, 3D-SoC partitioning & context aware STA.Conferences- Presenter, chair, committee and/or organizer at international (SNUG, VARI, CDNLive) and internal conferences; SNUG2009 best paper

Designed a very low power mixed-signal ASIC (0.35µ HighVoltage process). This single chip solution is driving mobile phones color active-matrix Liquid Cristal Display.Managed and trained a team of 6 digital engineersOrganized the digital activities (tasks splitting, resources, schedule, tracking), cooperation with the analog teamFeasibility study, chip floorplanning, new digital architecture definition, specificationsRTL design, verification, synthesis, place & route, STA, silicon wake-up.Deployed digital design practices and ensured high quality execution

I started as Static Timing Analysis (STA) engineer on a key project and became quickly one of the few STA experts at Ericsson, supporting projects company-wide. I extended my expertise to the rest of the design flow.Technical roles: STA, timing closure, place and route, synthesis, RTL redesign for quality and design. Offsite STA support & teacher and ASIC technical expert support. ASIC vendor/foundry technical interface.Technologies: IBM/LSI/Philips 180/130/110nm & FPGATechnical specificities: 12 silicon projects/chips, up to 3.2M row logic gates, 5.6Mbit of on chip memory, 270MHz, multi-clock My roles in the projects evolved quickly to technical leader positions, I also had the chance to setup and managed the EADP international and multi-team project.I learnt a lot from the 12 silicon projects I worked on in Sweden, Norway, Germany and Italy: management styles & techniques, inter-cultural conflicts, multi-site technical organization.Roles: ASIC leader, project manager, Request For Quotation, pricing and IP reuse contract negotiations

Digital ASIC designer in the Microelectronics section of the Control, Data and Power division (Noordwijk - The Netherlands)Worked on the next generation ESA ground-spacecraft communication component.Designed, in VHDL, the telecommand decoder core and created self-checking test benches for the decoder.

Digital ASIC designer in the Digital Media Broadcasting (DMB) department (Caen - France)Worked on an MPEG2 decoding component for digital TV. Designed a spy-bus (snoopy-bus) in VHDL which allowed study and evaluation of the component.