Nidhin George Email & Phone Number

"Success depend on how you learn, not on when you learn."Verilog | System Verilog | Universal Verification Methodology | Assertion Based Verification using SVAFSM based design | Simulation Code | Coverage Functional Coverage Synthesis | Static Timing Analysis (STA) | RTL Coding | Digital electronics | Digital design | Mentor Graphics-Questasim | Intel-Quartus Prime Lite | ModelSimLinux | WindowsThe strong desire to start career in Semiconductor Industry for which I am getting trained in VLSI course. The willing to work in a challenging position with a growing organization where I can utilize my technical and interpersonal skills and enhance the same.

Listed skills include Rtl Design, Systemverilog, Semiconductors, Intel Quartus Prime, and 12 others.

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  Amal Jyothi College Of Engineering

  Electrical, Electronics And Communications Engineering