Nikhil Somashekar Murthy Email & Phone Number

Mountain View, CA, US

San Jose, California, United States

Greater Boston Area

• Develop and own the Floorplanning methodology for a sub-system delivering floorplan collaterals to partition owners.
• Manage and own the back-end flow (synthesis, place and route, clock tree synthesis, Static Timing Analysis, etc.) for multiple blocks of sizes up to 1M cells
• Own the Physical Verification process for a sub-system which involved analyzing DRC (Design Rule Check) and LVS (Layout v/s Schematic) results and automated the process of layout fixes.
• Implement Engineering Change Order (ECO) for PnR (Place and Route) blocks and perform physical verification including timing closure, clock and layout closure.
• Perform Reliability Verification (EM, Self-Heat and IR Drop Analysis) and Signal Integrity/Crosstalk analysis.

Hudson, Massachusetts

• Compared different RTL models by running Synthesis, Place and Route, Primetime (with extract) and Caliber at the partition level and analyzed the design for quality (Shorts, Worst Negative Slack, Total Negative Slack.
• Automated the Synthesis, Place and Route and the Verification flow in Pandora.
• Developed scripts in TCL and Perl to identify issues and improve quality of design.

Karnataka, India

Responsible for developing remote monitoring systems for embedded applications using the LabVIEW graphical development tool.

Master'S Degree, Electrical Engineering, 3.78/4

Specializing in Backend VLSI Design

Bachelor Of Engineering (Be), Electrical And Electronics Engineering, 9.89/10