Part of Adaptive and Embedded Computing Group (AECG) at AMD (through Xilinx acquisition).I am responsible for all Xilinx Fabric Debug IPs, Vivado IPs for ACAP SoC devices which includes PS and AI Engine.

• Key responsibility involves mentoring, coaching, motivating and hiring to build high performance team • Responsible for all Xilinx Logic debug IPs and Vivado IPs for ARM based processor sub-system (PS), Platform Management Controller (PMC) and AI Engine of the Versal ACAP devices• Engaging with cross functional teams across multiple geographies to define Logic debug IP roadmap and playing a key role in defining debug solution for E&P market• Engaging with SoC architecture team and defining solution for next gen PS based SoC solution• Gathering requirements from marketing, defining specifications, and ensuring project execution to meet project schedule • Defined processes in the team which ensures quality of the deliverables

• Solution for next generation of products and devices. I was responsible for shaping up solution for Versal PS wizard and AI Engine IP.• Solution for next generation debug solution. I was responsible for AXI4 based debug hub implementation which is the backbone of Versal debug solution.• Architect, spec definition and implementation of High-Performance Debug Hub for Versal device family• Conceptualized and architected Debug Interface Module for usage in PCIe and DDR controller debug solution• Interacted with architecture team to define spec to model Versal CIPS and AI Engine IPs in Vivado IP catalog • Implemented custom logic to improve timing of AI Engine to/from PL interfaces and make the interfaces AXI4-Stream compliant • Mentored team to model Versal CIPS IP in Vivado

• Xilinx labtools (Chipscope) IP design. I have developed the JTAG to AXI master IP and numerous features of ILA and System ILA.• System level debug IP showcasing transaction level details, protocol and performance analysis• System ILA IP for system level debug solution in Vivado design suite• JTAG to AXI IP in Xilinx Vivado debug IP solution• ILA transitional storage feature development • Mentored team to model Zynq MPSoC IP in Vivado design suite • Interrupt controller template for Vivado Create Import Peripheral wizard for select customer usecases• Timing closure of complex systems.• Embedded/Video system design; Subsystem design, validation and analysis.• Created all the AXI4-MM and AXI4-Stream templates for Vivado Create peripheral wizard.

• Xilinx EDK/XPS based System/Subsystem design, validation and analysis.• Designs for Xilinx EDK XPS Base System Builder• AXI4-MM, AXI4-Lite, AXI4-Stream templates generation from Vivado Create Import Peripheral wizard• Vivado and EDK XPS IP for Zynq Processing System 7000

• Resolver Angle Digital Demodulation Scheme• Design of Discrete IO FE• Testbench for MIL-1553B IP core• Testcases and Testbenches development for Flight Control System for DO-254 certification

• Emulation of microprocessor 65CE02 FPGA• Emulation of microprocessor 8086 on Altera cyclone-II FPGA• PCM telemetry processor using PCI Express bus architecture