supporting Intel's Imaging and Camera Technologies Group (ICG) which develops the Next Generation Pre-Silicon Image Processing Unit (IPU). Verification in digital signal processing field.Knowledge of block level functional verification, developing test bench using System Verilog/ UVM. Write test plans to hardware image processing blocks, debug system Verilog and VHDL designs. In addition, debug C++ programs which uses as reference to the design.

Responsible on solving integration related problems, enabling different ingredients and flows, upgrading new design tools and working scripts in perl,python,cshell,system verliog on linux environment .