Experienced EDA Hardware Engineer proficient in optimizing semiconductor design methodologies and ensure proper design flows. Good knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification. Well versed with Design Rule Checks and Layout verification. Strong knowledge and experience in standard place and route flows Synopsys and Innovus Cadence flows. Good automation skills in PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools.EDA Tool : Cadence Innovus, Synopsis Fusion compiler, Caliber and ICV