Niravkumar Patel Email & Phone Number

Chandler, Az, Us

Noida, Uttar Pradesh, In

Santa Clara, California, Us

ASIC IP Verification Engineer:• Defined and developed scalable and reusable block, subsystem, and verification plans, test benches, and the verification environment to meet the required level of coverage to confirm architecture specifications. • Wrote directed and constrained-random tests, reusable System Verilog Assertions (SVAs), and Covergroups for coverage-driven verification. • Developed and delivered the HVM test contents to successful SoC Tape-ins as well as provided support to the post-silicon team. • Defined and tracked detailed test plans and also drove various reviews of TestPlans with design engineers, architects, and stakeholders to ensure first-pass silicon success. • Replicated, root-caused, and debugged the failures in the design, partnering with the design and architect team. • Responsible for constantly finding a better way to architect TestBench such that data transfer and sharing between TestBench components is done easily and promotes maintenance and reusability of the TestBench codes.

Santa Clara, California, Us

IP Design Engineer: • Designed the DDR memory controller to meet timing, performance, and power requirements. • Integrated memory controller into SoC/test chip and also provided support to ensure quality requirements and specification. • Wrote design specifications and worked closely with the physical design team to close timing and placeand-route issues. • Actively participated in test-chip/SoC power-on and helped the post-silicon team in debugging, routecause, and fixing the failures during the power-on time. • Oversees definition, design, verification, and documentation for IP development and support the crossfunctional teams. SoC Design Engineer:• Executed design integration of various design IPs and sub-systems into SoC-level design. • Responsible for RTL coding, simulation, and debugging for SoCs. • Carried out all aspects of the SoC design flow from high-level design to synthesis, equivalence checking, timing, and power to create a design database that was ready to consume by the backend team. • Analyzed weekly regression results of responsible units/partitions at the SoC level. • Oversees definition, design, verification, and documentation for SoC development and provides support to cross-functional product teams.

Chandler, Az, Us

• Responsibilities include digital IP top-level integration and RTL and gate-level verification.• Verification lead responsibilities include verification schedule development, assignment and monitoring of tasks to team members, reporting project verification status to product team and management • Experience with ECO flow for fixing control logic and datapath bugs. Formally verify the fixes using Synopsys Formality at full-chip level for equivalence checking of RTL to Gate level design.• Coordinate with the IP Design & Verification team and Architect on design issues and bug fixes. • Generate patterns using custom tool for production testing of silicon on Tester.• Debug failures, run regression and modify/develop tests as per requirements.• Hands on working experience of SystemVerilog Environment.• Working experience of various protocol integration and verification like I2C, ICAP, OCMP, UART etc• Provide support to cross-functional product teams (Product/Test, Architecture, Applications and Development Systems) to successfully release new PIC microcontroller families to production.

San Jose, Ca, Us

Master Of Science (Ms), Electrical Engineer

Bachelor Of Engineering - Be, Electronics & Communication