Nirav Toliya
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Nirav Toliya Email & Phone Number

Lead Software Engineer (Verification IP R&D) at Cadence Design Systems at Cadence Design Systems
Location: Ahmedabad, Gujarat, India 5 work roles 2 schools
1 work email found @nvidia.com LinkedIn matched
4 data sources Profile completeness 100%

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Work email n****@nvidia.com
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Current company
Cadence Design Systems
Role
Lead Software Engineer (Verification IP R&D) at Cadence Design Systems
Location
Ahmedabad, Gujarat, India
Company size
10 employees

Who is Nirav Toliya? Overview

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Quick answer

Nirav Toliya is listed as Lead Software Engineer (Verification IP R&D) at Cadence Design Systems at Cadence Design Systems, a company with 10 employees, based in Ahmedabad, Gujarat, India. AeroLeads shows a work email signal at nvidia.com and a matched LinkedIn profile for Nirav Toliya.

Nirav Toliya previously worked as Lead Software Engineer at Cadence Design Systems and Software Engineer at Cadence Design Systems. Nirav Toliya holds Master Of Technology (M.Tech.), Visual Information Processing And Embedded System Engineering, 8.93 from Indian Institute Of Technology, Kharagpur.

Company email context

Email format at Cadence Design Systems

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{first_initial}{last}@nvidia.com
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AeroLeads found 1 current-domain work email signal for Nirav Toliya. Compare company email patterns before reaching out.

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Profile bio

About Nirav Toliya

Nirav Toliya is a Lead Software Engineer (Verification IP R&D) at Cadence Design Systems at Cadence Design Systems. He possess expertise in matlab, data structures, computer networking, embedded systems, opencv and 11 more skills. He is proficient in English, Hindi and Gujarati.

Listed skills include Matlab, Data Structures, Computer Networking, Embedded Systems, and 12 others.

Current workplace

Nirav Toliya's current company

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Cadence Design Systems
Cadence Design Systems
Lead Software Engineer (Verification IP R&D) at Cadence Design Systems
sweden
Website
cadence.se
Employees
10
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5 roles

Nirav Toliya work experience

A career timeline built from the work history available for this profile.

Asic Power Engineer

Nvidia

Bengaluru Area, India

  • Member of an Applied Power Architecture (APA) team, which develops a tool to estimate Tegra SOC’s power under various use case scenario and helps to make product level decisions.
  • Role in Power Estimation Tool: - Implemented various features in Power Estimation tool and enhanced tool functionalities for upcoming Tegra SOCs. - Created infrastructure to scale chip level use case power to platform.
  • Role in NVIDIA Tegra SOC’s Power Modelling: - Responsible for developing and maintaining dynamic power models for various GPU intensive use case scenarios. - Correlate and Calibrate dynamic power models of integrated.
Jul 2016 - Apr 2019

Trainee

Nokia Siemens Networks

Rajkot Area, India

I was a trainee in NSS Department,VODAFONE.

Dec 2012 - Mar 2013
Team & coworkers

Colleagues at Cadence Design Systems

Other employees you can reach at cadence.se. View company contacts for 10 employees →

MK Mayank Kataria Mayank Kataria Colleague at Cadence Design Systems South Delhi, Delhi, India, India View → MC Mayank Chaturvedi Mayank Chaturvedi Colleague at Cadence Design Systems Bengaluru, Karnataka, India, India View → SG Sanjib Ghosh Sanjib Ghosh Colleague at Cadence Design Systems Fremont, California, United States, United States View → SG Sandeep Gupta Sandeep Gupta Colleague at Cadence Design Systems San Jose, California, United States, United States View → HZ Haiqing Zhao Haiqing Zhao Colleague at Cadence Design Systems San Jose, California, United States, United States View → RH Rory Humphries, Ph.D Rory Humphries, Ph.D Colleague at Cadence Design Systems Cork, County Cork, Ireland, Ireland View → JC Jade Cravy Jade Cravy Colleague at Cadence Design Systems San Jose, California, United States, United States View → LW Lee Williams Lee Williams Colleague at Cadence Design Systems Santa Clara, California, United States, United States View → TA Tanmay Aron Tanmay Aron Colleague at Cadence Design Systems New Delhi, Delhi, India, India View → SL Sohini Lone Sohini Lone Colleague at Cadence Design Systems Pune, Maharashtra, India, India View →
2 education records

Nirav Toliya education

FAQ

Frequently asked questions about Nirav Toliya

Quick answers generated from the profile data available on this page.

What company does Nirav Toliya work for?

Nirav Toliya works for Cadence Design Systems.

What is Nirav Toliya's role at Cadence Design Systems?

Nirav Toliya is listed as Lead Software Engineer (Verification IP R&D) at Cadence Design Systems at Cadence Design Systems.

What is Nirav Toliya's email address?

AeroLeads has found 1 work email signal at @nvidia.com for Nirav Toliya at Cadence Design Systems.

Where is Nirav Toliya based?

Nirav Toliya is based in Ahmedabad, Gujarat, India while working with Cadence Design Systems.

What companies has Nirav Toliya worked for?

Nirav Toliya has worked for Cadence Design Systems, Nvidia, Indian Institute Of Technology, Kharagpur, and Nokia Siemens Networks.

Who are Nirav Toliya's colleagues at Cadence Design Systems?

Nirav Toliya's colleagues at Cadence Design Systems include Mayank Kataria, Mayank Chaturvedi, Sanjib Ghosh, Sandeep Gupta, and Haiqing Zhao.

How can I contact Nirav Toliya?

You can use AeroLeads to view verified contact signals for Nirav Toliya at Cadence Design Systems, including work email, phone, and LinkedIn data when available.

What schools did Nirav Toliya attend?

Nirav Toliya holds Master Of Technology (M.Tech.), Visual Information Processing And Embedded System Engineering, 8.93 from Indian Institute Of Technology, Kharagpur.

What skills is Nirav Toliya known for?

Nirav Toliya is listed with skills including Matlab, Data Structures, Computer Networking, Embedded Systems, Opencv, Embedded C, Digital Electronics, and Vlsi.

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