Nick Spence Email & Phone Number

Eindhoven, Noord-Brabant, NL

Eindhoven, Noord-Brabant, NL

• Managed a group of 7 engineers in a multi-disciplined team providing digital enablement throughout the RF organization. Responsibility ranged from solution architecture, design, PCB creation, embedded and PC based.
• Architected, implemented and supported Xilinx Zynq MPSoC based 115 Gbps radio frame playback and capture system
• Analyzed project started with a contractor, identified architectural oversights, simulation mistakes and design errors
• Performed system simulation to address architectural and implementation decisions, and to validate final product design
• Used Xilinx Vivado tools to synthesize Verilog RTL, JESD204 blocks, floorplan, debug and perform timing analysis
• Designed CPU interface register system to handle timing interactions in a multi-clock domain environment

Austin, Texas, US

• Windows 9-axis motion sensor
• Instigated IMU platform for tier 1 PC customer to market Freescale sensors and meet marketing commitments
• Identified and engaged sensor fusion software provider, managed interface and software integration
• System was competed in time to meet customer design-in windowMotion cube
• Created fun innovative marketing tool to demonstrate Freescale accelerometers, widely adopted by the sales team

Austin, Texas, US

• Responsible for learning GPON (Gigabit Passive Optical Networking) MAC domain expertise, creating a Linux device driver for the GPON MAC layer and supporting its use by internal and external customers. Ported Linux BSP.
• Traveled to domestic and international customers and FSAN interop events to demonstrate interoperability of the GPON chipset and software. Successfully resolved issues as needed to complete testing and win 3 customers
• Created an FPGA based GPON analyzer as a side project. Designed hardware and FPGA code enabling the source of a customer problem to be located and the hardware issue to be identified

Austin, Texas, US

• Managed a 10-person multi-disciplinary system applications team supporting the silicon development, marketing and sales teams, and external customers. Responsible for: the design and sourcing of evaluation and.
• MSC7120 GPON Evaluation board was functional and running u-boot within two days of delivery of the MSC7120 silicon samples. Co-operative board design and software implementation enabled the customer to meet their.
• Enabled the silicon design team with boards, debuggers and engineering support to perform silicon validation tests of all key functionality with the first evaluation board

• Managed a 12-person multi-disciplinary team to specify, design, build and support evaluation boards for next generation set top box solutions using the Motorola designed single chip audio/video MPEG integrated circuit.
• Completed verification and customer evaluation platforms. First pass success completed ahead of schedule with customized software debug monitor and early VxWorks port
• Rebuilt and mentored team of diverse engineers to grow the software team and co-ordinate offshore software resources

• Developed two generations of multi-plane graphics devices to display video and graphics on a television display. Responsible for functional specification, algorithmic evaluation, RTL design, implementation to layout.
• Created SDRAM controller to support unlimited length bursts and intelligent bank swapping. Captured the design in Verilog and simulated with VCS. Synthesized with Synopsys and performed static timing analysis with.
• Specified the graphics overlay block design for the second generation and reduced the gate count using Module Compiler. Specified improvements in the host interface and the BitBLT module

• Supported key customers using the ASIC CAD flow and resolved design, prototype and test issues. Worked with design group to specify, test, document and support new I/O cells, APLL blocks and technology:
• Customer interface for three key customers resolving design and CAD issues to develop customer intimacy and active involvement through test and debug to resolve design problems
• Project lead for H4EP technology. Coordinated with design and CAD groups to modify front and back end CAD flows. Development completed ahead of 10X cycle time reduction goals. 45% of new business used H4EP within 1 year

• Strengthened the CAD simulation and test team to integrate commercial and internal tools into a unified ASIC CAD flow used by internal and external customers:
• Researched timing analyzer tools and designed Verilog models to support Veritime and Verifault using UDP models
• Worked with a design team to design JTAG cells and a memory BIST flow that was compatible with ATPG (Automatic Test Pattern Generation) tools, resulting in the awarding of five patents

Digital design engineer designing, evaluating and implementing DSP algorithms. Enabled and supported Mentor Graphics CAD system specializing in digtial functional and fault simulation. Awarded Plessey "Young Engineer of the Year 1987".

Mba, Business Administration

Msc, Electronic Engineering, Software Engineering

Bsc, Electronic Engineering