• First engineer recruited to build a new high availability and multi-card ATCA chassis, including switchingfabric for the data center inter-connect and cloud computing market.• Contributed to a number of key features to deliver a high quality product under tight time constraints tolarge content provider and service provider customers. This included a carrier grade and highly scalablesolution combining: packet, optical and NFV applications.• Collaborated closely with developers across multiple sites including; Ottawa, Belfast and Wuhan (China).• Identified and defined selection criteria to select third party development partners for; messaginginfrastructure, application to manage the northbound interface, and target Linux OS.• Selected Apache Qpid and then designed API’s to the messaging infrastructure used by all processes inthe system.• Designed initial Architecture of the early bring up of the modules, using a Discovery process and definingits redundancy behavior.• Designed the Multi Chassis configuration bring up.• Initial design of the software upgrade infrastructure, with no traffic loss.• Defined and implemented rules for the AAA behavior of the system.• Designed strategy to perform seamless upgrade/transition to new generation CMM modules (the heart ofthe system) in the field.• Completed the IBM (in band management) design and bring up on our Universal Forwarding Modules andthe ROADM’s after a major porting effort.• using WindRiver Linux, C++, Python, Qpid, Tail-f Confd, scripting

Enhanced and maintained the statistics system for the BIGIP networking product.Role included:- Take over the statistics functionality for the development team.- New feature design and implementations.- Resolve customer issues referred to the development team.- Bug fixes of the current code base.

• Early member of the startup team. Responsible for overall architecture, design and implementation of the embedded feed handlers to accept high speed real time exchange feeds from the Option Price Reporting Agency. Early trials at key customers such as Goldman Sachs showed significant ability to manage high data rates.• Early adopter of the new Intel Nehalem multi core architecture platforms. Responsible for migration and early bring up of the feed handlers on the new Intel Platform at their Parcepany development site. Planned and performed performance evaluation and tuning of the Feed handlers on the Nehalem Linux platform at the Intel performance labs. Early results show a significant improvement, a three times performance improvement for OPRA to 3.9 Million Messages per second. This allowed for the company to market the superior performance of the feed handlers.• Designed and implemented other real time book feeds, both TCP connected and Multicast generated feeds, DirectEdge and BATS respectively, targeted for Linux CentOS platforms.• Using ‘C’, pthreads, linux, exploiting the multicore platform architecture and Agile development process.

Project to program flash of an embedded NEC microcontroller (uPD70F3714) connected to a GUI application running on a PC to download an image in the field.

• Linux 2.6 embedded driver development for the ASI (Advanced Switching Interconnect) set of new fabricASIC’s. Developed a design for Fabric Event handling. This involved the interrupt handling capability forprocessing of events in the Switching Fabric, managing the ASIC multiple events processing.• Developed the capability to update the SROM of any node in the fabric. This could be the ASI bridge hostas well as the switches in the network.Responsible for the embedded Linux bring up for the evaluation module developed to show the capabilitiesof the Mindspeed Traffic Stream Network Processor. Led the Linux effort for the embedded host system. Started the software project and delivered the first phase on schedule.

• Hired to lead a team of 7 for a new 12/24 port Infiniband switch project. Defined the requirements, and the project scope. Specified switch functionality, designed and led the implementation. Delivered the switch in 12 months with multiple ASIC spins which allowed the company to create first stream of revenue ($500,000 in a short time).• Reported directly to the VP of software. Hands on management for complete cycle of project, from conception to delivery to customers.• Developed/implemented Linux Kernel based Packet driver, designed and ported existing Linux applications, debugged the ASICs; wrote ASIC workarounds.• Drove the switch thru conformance testing and it has been certified as Infiniband compliant by the IBTA. Led the conformance testing at two IBTA plugfests. Also responsible for having the switch pass the “IBM Server Proven” program. Thus IBM has this product on the approved vendor list allowing the company exposure to the IBM client base.• Member of a team investigating the next generation switches for 10G ethernet. Evaluating existing third party software vendors; L2 and L3 functionality.• Target Processsor PPC405 ; Linux Target OS; C Language. Use of RPC; Gdb; CVS

• Finalized requirements and then designed and implemented the Bellcore GR 253 compliant SONET clocking for the backbone ring. The implementation supports SSM messaging and ring clock recovery on failures as specified by the Bellcore standard. This feature included the management of clocking/timing module.• Designed and implemented the Port Manager which provided the management of all port configurations. The configurations are distributed to all cards in the ISTN node.• Instrumental in defining the IPC communication for the ISTN switch as a part of the infrastructure software.• Responsible for RIO (Dual Ring I/O) redundancy feature integration.• Defined the requirements and the design of the 1:N redundancy feature for DS1 and DS3 interfaces.• Designed the 1:1 DS1 redundancy feature.• Target Processors MPC860, MPC750; C Language; VxWorks; Clearcase.