• More than 18 years of Networking chips (Ethernet switches) development through the entire development cycle• More than 15 years of ASIC development experience in aspects of architecture and definition, chip design, verification and validation• More than 10 years of experience in time synchronization over Ethernet switches (definition, development, validation and customer support)• 4 years of hands on experience in customer support worldwide focused on USA, China and Taiwan. • 2 years leading the security concept, design, verification plan and threat analysis in the SOCPatents: - Parser and modifier for processing network packets (9276851)- Method and apparatus for transmit time timestamping (11689440)- One-step timestamping in network devices - MAC (11575495)- One-step timestamping in network devices - PHY (11818241)Publications- Dynamic one-step/two step timestamping per packet in network devices (20230269018, 20230269161)- Transmission of packets at specific transmit time with preemption (20230072376)- Timestamping over media independent interfaces (20230269015)- Timestamping for multiple synchronization domains in a network deviceAreas of Expertise include:• Multidisciplinary knowledge in embedded systems, hardware, and software• Innovative, quick learner, independent and strong technical leadership• Working in global teams from multiple nationalities• Experience with Customer relationship and support• Experience with full chip development lifecycle from product definition to production and beyond