* NPI product launch at HBM customers* System Debug and Solution Development* Software development

* HBM4 DFT planning and specification feasibility evaluation.-- Ongoing DRAM security development-- DRAM Telemetry function development (temperature, stack health, variation)-- Data Aligner Function* HBM3 development and validation-- Drive new component tests for TSV and data aligner timing loops (DLL, TSV receiver, transmitter, PD, Data Aligner blocks)-- Understand customer system failure signatures and tie failures to component testing methods to screen.-- Power reduction exploration for developing best in class HBM3 power/performance trade-offs-- Drive design of new features unique to Micron HBM3+ products-- Validate design of data aligner circuit in sim and silicon.-- Train and mentor newer hires on basics of various DRAM circuits (voltage supply, training & calibration, tuning circuits) as well as DFT circuits to enable testing methods.* HBM2E productization-- Debug several testing method issues with MBIST circuits* Micron - Purdue Technical Ambassador-- Coordinated Fall 2022 and assisted with Fall 2023 recruiting trip and is continued technical expert for Purdue faculty & student industry involvement-- Helped coordinate continued recruiting effort and presentations to Purdue students and classes-- Advised Purdue VP's, and semiconductor faculty members on skills gaps, technical expertise and need required to fill the fabs and engineering roles for the semicondutor act related spending in the US.

Driving Micron and industry-wide improvements in DRAM security:* 🔨 Rowhammer circuit effectiveness, efficiency, general function* Improved verification and validation methods (timing and logic simulations, component and in-system silicon testing and characterization)* Involved in Micron IP development as well as definition phase of JEDEC hammer specification changes (Refresh Management, Directed Refresh Management, Adaptive Refresh Management, Per Row Tracking and other related security concepts still pending)* Drive global Design, Verification, and Product Engineering task forces with goal of preventing future potential DRAM exploitation methods.

- Coordinated Multi-functional Global Task Force in charge of improving DRAM security against Row Hammer Attacks while developing security circuits, verification and testing methods, as well as IP for Micron's next generation DRAM designs.- Involved with developing circuits from initial concept, to behavioral and C++ models, verification flows and finally silicon validation during production volume ramp.- Developing DFT protection mechanisms to prevent escalated DRAM privileges by bad actors.

- Base standard circuit design modification recommendations - transferring methods used in Mobile products to Commodity and Compute Product lines (temperature sensor, IB calibration, static duty cycle trimming)- Deploy initial Probe and Test coverage methods for newly developed circuits- Evaluated new DFT methods used to improve product performance and yields.- DFMEA (Design Failure Mode and Effect Analysis) process completion where applicable.- Coordination between DRAM development teams to keep products families and production lines aligned with respect to circuits used, pattern coverage, and product quality.- Establishing best known methods and standard practices for use with several DRAM teams.

Developed a new team of product engineers tasked with aligning the technical, design and production aspects of Micron's various Mobile DRAM products. Responsible for: - Early LP3 and LP4 products standard circuit selection based on silicon performance metrics- General Design and DRAM Standard circuit modifications and improvements- Test validation coverage and testing method improvements for standard circuits.- Established and communicated new and more efficient methods of product debug and data analysis.- Coordinating between various Micron DRAM development teams to keep products, production lines, and engineering methods aligned.

* Mobile LPDDR2 product engineer team lead for 4Gb part.* Mobile LPDDR and LPSDR product engineer team lead for 512Mbit devices. - Led a team of engineers responsible for mobile memory research and development. - Coordinated across several functional groups within the company to get parts production ready and yielding including (Fab Production, Probe Test, Assembly, Backend Test, Planning, QA, Applications and Marketing groups).

Integral part of a team tasked with research and development work on several high density first generation DDR3 part types (2Gb and 1Gb). - Developed PERL scripting program to correlate failures through several backend test steps. - Made several circuit edits and schematic changes for Micron's first 2Gb DDR3 design using 3L metal design.

Built and maintained the Sled2Sled.com snowmobile hill climb website for RMSHA competitions.- Rebuilt original site to support more secure and interactive content for racers and fans- Updated photo galleries, race data, results, blog, as well as track web page use statistics for analysis.- Drive ad revenue to support the site with several ad banners and creative marketing methods.- Support Wordpress content management system and SQL database of race results.- Google+, Facebook, and Twitter feed integrations

Built up knowledge on the DRAM manufacturing industry with intern experience working on 512Mb DDR production part and 1Gb DDR2 development part. Involved with many short term debug projects and documentation (Testing methods, PFA - product failure analysis, and defect characterization).

Worked on various projects as a co-op including:* Terminal Engineering: - Electrical Preventative Maintenance - SVP (Small Volume Prover)* Pipeline Engineering: - Safety Group Engineering - PLC Programming for Various Pipeline Stations - DRA product analysis (drag reducing agent)