Lead multiple 0->1 products in AI Platforms at meta, growing them into successful platforms with over 100 internal customer teams. Resulting in multiple product launches with over $100M win for Meta and large improvements in company topline metrics like monthly active users.

• Architecture evaluation - Performance/Area/Power evaluation for algorithm implementations - Trade of analysis of new design features - Construct corner-case congestion stress tests for interconnect• Architecture Modeling - Maintain/Updating consistent arch model to software and hardware team - Creating new representation to adjust for silicon characterization results - Optimize performance of model generation software - Coordinate arch releases without interrupting development in software team• System specification - Combing hardware design specification/constraint from entire chip to form single coherent system level boot specification - Created new packed format and assembler/disassembler tool - Work with software team to implement specifications• Software - Algorithm specification for -- Power Estimation -- Power Optimization -- Configuration Generation - Managed timely completion of software implementation with remote and on-site software developers• Verification - Chip level - Small custom layout blocks

• Architecture modeling - Image processing Pipeline - Video output pipeline - Mpeg Mode Decision• Firmware - Reference microcode development• Verification - Fullchip - Large SoC Blocks (ARM/AMBA/IO, Entire Image processing pipeline) - Small functional Block testing (image filters, controllers...)• Tool Flow Optimization - Increase testing efficiency - Reduce Server Farm load from large regressions reruns - Integrate coverage analysis with regression runs

• Lead the planning and execution of all aspects of annual conferences with thousands of attendees• Managing a team of ~50 volunteers• Make spending decisions• Work with HYSTA board members and other directors on - design of conference program - secure high profile speakers - secure sponsors

Computer Science department, UC BerkeleyInteractive FPGA design environment. Intended Ph.D. dissertation (on Hold)• Research previous approaches to solving CAD tool turnaround time.• Design, Implementation, and evaluation of novel CAD algorithms in an interactive design environment.• Tie together different software pieces to form a complete tool-flow

Computer Science department, UC Berkeley7 semesters in various Computer Science and Electrical Engineering classes. Beginning as an undergrad sophomore.• Classes include: EECS150, CS61C, EECS40 • Assisted and instructed undergraduate students in classroom and laboratory settings• Generated materials for labs, lectures, and exams• Gave complete lab and regular lectures• Taking new projects from concept to implementation as a head TA• Helped to revise course curriculum to better prepare students for the job market

Computer Science department, UC BerkeleyCalinx instructional board design.• Collaborated with Xilinx during specification phase of ver1, 2 of Calinx Instructional Board • Debugged board design of Calinx ver1• Firmware development and debugging for peripherals• Developed materials for class projects using the Calinx board

Berkeley Wireless Research CenterCollaborative Software Defined Radio project with Infineon• Cooperative work with visiting scholar and research team from Infineon.• Detailed architectural implementation of SIMD processor core cluster.• Designed and implemented different verification approaches.• FPGA based emulation using BEE (Berkeley Emulation Engine)

S.T. Microelectronics, Berkeley R&D lab (summer internship)SoC test chip design• Tensilica Xtensa processor emulation on FPGA• Design custom ASIC peripheral block• Integration and testing of processor and peripherals for SoC design