Neeraj Paliwal Email & Phone Number

Responsible for leading the entire Synopsys IP product portfolio, developing the strategy, business plan, resources, programs, and processes to meet the financial plan. The Synopsys Silicon IP product line is a fast-growing multi-billion-dollar business spanning memory, logic & I/O, processors, security, and interface IP (digital & PHY).

United States

Leading the Silicon IP Business Unit, including the Interface and Security IP products

Led the Security IP teams to build industry’s #1 Cryptography Silicon IP supplier. Over 250 design wins during the last three years in the datacenter, edge, automotive and defense segments.

San Francisco

Kryptos developed an end to end secure military-grade mobile platform based upon Android AOSP. Responsible for all aspects of the startup, from starting business entity to architecture details. Primary focus on government and financial institutes. Completed IP transfer sale to customer in October 2017.

Hamburg, Germany

◼︎ Responsible for the product development for 1Billion$+ revenue Identification business. Main focus on building an engineering organization that delivers products with the quality and speed required by Identification customers. ◼︎ Led global engineering teams in the areas of Cryptography, RF/Contactless Technologies, Secure Element IC, Secure ASIC, NFC.

Bangalore, India

◼︎ Led central engineering teams in Netherlands, Germany, Belgium, UK, France, and India. ◼︎ Built lean, efficient, and transparent central design engineering teams of 250+ engineers worldwide. This enabled NXP business lines to meet their time-to-market requirements.◼︎ Led NXP's India operations, built 10 NXP labs at engineering universities across India.

Austin, TX

◼︎ Started with IBM as an engineer in Chip Integration team for the first generation CELL processor chip (SONY PlayStation3). Led the final verification efforts for overall 1Billion+ transistors on CELL chip.◼︎ Led design tools and methodology team for IBM's gaming processors supporting 600+ designers worldwide working on SONY Playstation3 and Microsoft.

Austin, TX And Dupont, WA

◼︎ Chip design methodology, physical design, and chip integration roles at Intel's 32-bit Microprocessor and 64-bit Chipset Groups◼︎ Started as Design Methodology engineer in DuPont WA and within four years progressed to lead Design Floorplan for 32-bit Intel Microprocessor (Tejas) in Austin TX.

Stanford Executive Program

Master'S Degree